Lines Matching refs:priv
102 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_clr_pend_irq() argument
104 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); in hix5hd2_i2c_clr_pend_irq()
106 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq()
111 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_clr_all_irq() argument
113 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq()
116 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_disable_irq() argument
118 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq()
121 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_enable_irq() argument
124 priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_enable_irq()
127 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_drv_setrate() argument
133 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
134 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
136 rate = priv->freq; in hix5hd2_i2c_drv_setrate()
137 sysclock = clk_get_rate(priv->clk); in hix5hd2_i2c_drv_setrate()
139 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); in hix5hd2_i2c_drv_setrate()
140 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); in hix5hd2_i2c_drv_setrate()
143 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
145 dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n", in hix5hd2_i2c_drv_setrate()
149 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_init() argument
151 hix5hd2_i2c_disable_irq(priv); in hix5hd2_i2c_init()
152 hix5hd2_i2c_drv_setrate(priv); in hix5hd2_i2c_init()
153 hix5hd2_i2c_clr_all_irq(priv); in hix5hd2_i2c_init()
154 hix5hd2_i2c_enable_irq(priv); in hix5hd2_i2c_init()
157 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_reset() argument
159 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_reset()
161 clk_prepare_enable(priv->clk); in hix5hd2_i2c_reset()
162 hix5hd2_i2c_init(priv); in hix5hd2_i2c_reset()
165 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_wait_bus_idle() argument
173 int_status = hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_wait_bus_idle()
183 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_over() argument
185 if (priv->state == HIX5I2C_STAT_SND_STOP) in hix5hd2_rw_over()
186 dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__); in hix5hd2_rw_over()
188 dev_dbg(priv->dev, "%s: have not data to send\n", __func__); in hix5hd2_rw_over()
190 priv->state = HIX5I2C_STAT_RW_SUCCESS; in hix5hd2_rw_over()
191 priv->err = 0; in hix5hd2_rw_over()
194 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_handle_stop() argument
196 if (priv->stop) { in hix5hd2_rw_handle_stop()
197 priv->state = HIX5I2C_STAT_SND_STOP; in hix5hd2_rw_handle_stop()
198 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); in hix5hd2_rw_handle_stop()
200 hix5hd2_rw_over(priv); in hix5hd2_rw_handle_stop()
204 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv) in hix5hd2_read_handle() argument
206 if (priv->msg_len == 1) { in hix5hd2_read_handle()
208 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
209 } else if (priv->msg_len > 1) { in hix5hd2_read_handle()
211 writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
213 hix5hd2_rw_handle_stop(priv); in hix5hd2_read_handle()
217 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv) in hix5hd2_write_handle() argument
221 if (priv->msg_len > 0) { in hix5hd2_write_handle()
222 data = priv->msg->buf[priv->msg_idx++]; in hix5hd2_write_handle()
223 writel_relaxed(data, priv->regs + HIX5I2C_TXR); in hix5hd2_write_handle()
224 writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM); in hix5hd2_write_handle()
226 hix5hd2_rw_handle_stop(priv); in hix5hd2_write_handle()
230 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_preprocess() argument
234 if (priv->state == HIX5I2C_STAT_INIT) { in hix5hd2_rw_preprocess()
235 priv->state = HIX5I2C_STAT_RW; in hix5hd2_rw_preprocess()
236 } else if (priv->state == HIX5I2C_STAT_RW) { in hix5hd2_rw_preprocess()
237 if (priv->msg->flags & I2C_M_RD) { in hix5hd2_rw_preprocess()
238 data = readl_relaxed(priv->regs + HIX5I2C_RXR); in hix5hd2_rw_preprocess()
239 priv->msg->buf[priv->msg_idx++] = data; in hix5hd2_rw_preprocess()
241 priv->msg_len--; in hix5hd2_rw_preprocess()
243 dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n", in hix5hd2_rw_preprocess()
244 __func__, priv->state, priv->msg_len); in hix5hd2_rw_preprocess()
252 struct hix5hd2_i2c_priv *priv = dev_id; in hix5hd2_i2c_irq() local
256 spin_lock(&priv->lock); in hix5hd2_i2c_irq()
258 int_status = hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_irq()
263 dev_dbg(priv->dev, "ARB bus loss\n"); in hix5hd2_i2c_irq()
264 priv->err = -EAGAIN; in hix5hd2_i2c_irq()
265 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
269 dev_dbg(priv->dev, "No ACK from device\n"); in hix5hd2_i2c_irq()
270 priv->err = -ENXIO; in hix5hd2_i2c_irq()
271 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
276 if (priv->msg_len > 0) { in hix5hd2_i2c_irq()
277 ret = hix5hd2_rw_preprocess(priv); in hix5hd2_i2c_irq()
279 priv->err = ret; in hix5hd2_i2c_irq()
280 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
283 if (priv->msg->flags & I2C_M_RD) in hix5hd2_i2c_irq()
284 hix5hd2_read_handle(priv); in hix5hd2_i2c_irq()
286 hix5hd2_write_handle(priv); in hix5hd2_i2c_irq()
288 hix5hd2_rw_over(priv); in hix5hd2_i2c_irq()
293 if ((priv->state == HIX5I2C_STAT_RW_SUCCESS && in hix5hd2_i2c_irq()
294 priv->msg->len == priv->msg_idx) || in hix5hd2_i2c_irq()
295 (priv->state == HIX5I2C_STAT_RW_ERR)) { in hix5hd2_i2c_irq()
296 hix5hd2_i2c_disable_irq(priv); in hix5hd2_i2c_irq()
297 hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_irq()
298 complete(&priv->msg_complete); in hix5hd2_i2c_irq()
301 spin_unlock(&priv->lock); in hix5hd2_i2c_irq()
306 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop) in hix5hd2_i2c_message_start() argument
310 spin_lock_irqsave(&priv->lock, flags); in hix5hd2_i2c_message_start()
311 hix5hd2_i2c_clr_all_irq(priv); in hix5hd2_i2c_message_start()
312 hix5hd2_i2c_enable_irq(priv); in hix5hd2_i2c_message_start()
314 if (priv->msg->flags & I2C_M_RD) in hix5hd2_i2c_message_start()
315 writel_relaxed((priv->msg->addr << 1) | HIX5I2C_READ_OPERATION, in hix5hd2_i2c_message_start()
316 priv->regs + HIX5I2C_TXR); in hix5hd2_i2c_message_start()
318 writel_relaxed(priv->msg->addr << 1, in hix5hd2_i2c_message_start()
319 priv->regs + HIX5I2C_TXR); in hix5hd2_i2c_message_start()
321 writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM); in hix5hd2_i2c_message_start()
322 spin_unlock_irqrestore(&priv->lock, flags); in hix5hd2_i2c_message_start()
325 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv, in hix5hd2_i2c_xfer_msg() argument
331 priv->msg = msgs; in hix5hd2_i2c_xfer_msg()
332 priv->msg_idx = 0; in hix5hd2_i2c_xfer_msg()
333 priv->msg_len = priv->msg->len; in hix5hd2_i2c_xfer_msg()
334 priv->stop = stop; in hix5hd2_i2c_xfer_msg()
335 priv->err = 0; in hix5hd2_i2c_xfer_msg()
336 priv->state = HIX5I2C_STAT_INIT; in hix5hd2_i2c_xfer_msg()
338 reinit_completion(&priv->msg_complete); in hix5hd2_i2c_xfer_msg()
339 hix5hd2_i2c_message_start(priv, stop); in hix5hd2_i2c_xfer_msg()
341 timeout = wait_for_completion_timeout(&priv->msg_complete, in hix5hd2_i2c_xfer_msg()
342 priv->adap.timeout); in hix5hd2_i2c_xfer_msg()
344 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_xfer_msg()
345 priv->err = -ETIMEDOUT; in hix5hd2_i2c_xfer_msg()
346 dev_warn(priv->dev, "%s timeout=%d\n", in hix5hd2_i2c_xfer_msg()
348 priv->adap.timeout); in hix5hd2_i2c_xfer_msg()
350 ret = priv->state; in hix5hd2_i2c_xfer_msg()
356 if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop) in hix5hd2_i2c_xfer_msg()
357 ret = hix5hd2_i2c_wait_bus_idle(priv); in hix5hd2_i2c_xfer_msg()
360 hix5hd2_i2c_reset(priv); in hix5hd2_i2c_xfer_msg()
362 return priv->err; in hix5hd2_i2c_xfer_msg()
368 struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap); in hix5hd2_i2c_xfer() local
371 pm_runtime_get_sync(priv->dev); in hix5hd2_i2c_xfer()
375 ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); in hix5hd2_i2c_xfer()
389 dev_warn(priv->dev, "xfer message failed\n"); in hix5hd2_i2c_xfer()
393 pm_runtime_mark_last_busy(priv->dev); in hix5hd2_i2c_xfer()
394 pm_runtime_put_autosuspend(priv->dev); in hix5hd2_i2c_xfer()
411 struct hix5hd2_i2c_priv *priv; in hix5hd2_i2c_probe() local
416 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in hix5hd2_i2c_probe()
417 if (!priv) in hix5hd2_i2c_probe()
422 priv->freq = 100000; in hix5hd2_i2c_probe()
425 priv->freq = HIX5I2C_MAX_FREQ; in hix5hd2_i2c_probe()
426 dev_warn(priv->dev, "use max freq %d instead\n", in hix5hd2_i2c_probe()
429 priv->freq = freq; in hix5hd2_i2c_probe()
434 priv->regs = devm_ioremap_resource(&pdev->dev, mem); in hix5hd2_i2c_probe()
435 if (IS_ERR(priv->regs)) in hix5hd2_i2c_probe()
436 return PTR_ERR(priv->regs); in hix5hd2_i2c_probe()
444 priv->clk = devm_clk_get(&pdev->dev, NULL); in hix5hd2_i2c_probe()
445 if (IS_ERR(priv->clk)) { in hix5hd2_i2c_probe()
447 return PTR_ERR(priv->clk); in hix5hd2_i2c_probe()
449 clk_prepare_enable(priv->clk); in hix5hd2_i2c_probe()
451 strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); in hix5hd2_i2c_probe()
452 priv->dev = &pdev->dev; in hix5hd2_i2c_probe()
453 priv->adap.owner = THIS_MODULE; in hix5hd2_i2c_probe()
454 priv->adap.algo = &hix5hd2_i2c_algorithm; in hix5hd2_i2c_probe()
455 priv->adap.retries = 3; in hix5hd2_i2c_probe()
456 priv->adap.dev.of_node = np; in hix5hd2_i2c_probe()
457 priv->adap.algo_data = priv; in hix5hd2_i2c_probe()
458 priv->adap.dev.parent = &pdev->dev; in hix5hd2_i2c_probe()
459 i2c_set_adapdata(&priv->adap, priv); in hix5hd2_i2c_probe()
460 platform_set_drvdata(pdev, priv); in hix5hd2_i2c_probe()
461 spin_lock_init(&priv->lock); in hix5hd2_i2c_probe()
462 init_completion(&priv->msg_complete); in hix5hd2_i2c_probe()
464 hix5hd2_i2c_init(priv); in hix5hd2_i2c_probe()
468 dev_name(&pdev->dev), priv); in hix5hd2_i2c_probe()
475 pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC); in hix5hd2_i2c_probe()
476 pm_runtime_use_autosuspend(priv->dev); in hix5hd2_i2c_probe()
477 pm_runtime_set_active(priv->dev); in hix5hd2_i2c_probe()
478 pm_runtime_enable(priv->dev); in hix5hd2_i2c_probe()
480 ret = i2c_add_adapter(&priv->adap); in hix5hd2_i2c_probe()
489 pm_runtime_disable(priv->dev); in hix5hd2_i2c_probe()
490 pm_runtime_set_suspended(priv->dev); in hix5hd2_i2c_probe()
492 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_probe()
498 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); in hix5hd2_i2c_remove() local
500 i2c_del_adapter(&priv->adap); in hix5hd2_i2c_remove()
501 pm_runtime_disable(priv->dev); in hix5hd2_i2c_remove()
502 pm_runtime_set_suspended(priv->dev); in hix5hd2_i2c_remove()
511 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); in hix5hd2_i2c_runtime_suspend() local
513 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_runtime_suspend()
521 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); in hix5hd2_i2c_runtime_resume() local
523 clk_prepare_enable(priv->clk); in hix5hd2_i2c_runtime_resume()
524 hix5hd2_i2c_init(priv); in hix5hd2_i2c_runtime_resume()