168 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)  in dw_readl()  function
259 		if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)  in __i2c_dw_enable()
300 	reg = dw_readl(dev, DW_IC_COMP_TYPE);  in i2c_dw_init()
363 		reg = dw_readl(dev, DW_IC_COMP_VERSION);  in i2c_dw_init()
391 	while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {  in i2c_dw_wait_bus_not_busy()
412 	ic_con = dw_readl(dev, DW_IC_CON);  in i2c_dw_xfer_init()
441 	dw_readl(dev, DW_IC_CLR_INTR);  in i2c_dw_xfer_init()
498 		tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);  in i2c_dw_xfer_msg()
499 		rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);  in i2c_dw_xfer_msg()
578 		rx_valid = dw_readl(dev, DW_IC_RXFLR);  in i2c_dw_read()
581 			*buf++ = dw_readl(dev, DW_IC_DATA_CMD);  in i2c_dw_read()
733 	stat = dw_readl(dev, DW_IC_INTR_STAT);  in i2c_dw_read_clear_intrbits()
743 		dw_readl(dev, DW_IC_CLR_RX_UNDER);  in i2c_dw_read_clear_intrbits()
745 		dw_readl(dev, DW_IC_CLR_RX_OVER);  in i2c_dw_read_clear_intrbits()
747 		dw_readl(dev, DW_IC_CLR_TX_OVER);  in i2c_dw_read_clear_intrbits()
749 		dw_readl(dev, DW_IC_CLR_RD_REQ);  in i2c_dw_read_clear_intrbits()
755 		dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);  in i2c_dw_read_clear_intrbits()
756 		dw_readl(dev, DW_IC_CLR_TX_ABRT);  in i2c_dw_read_clear_intrbits()
759 		dw_readl(dev, DW_IC_CLR_RX_DONE);  in i2c_dw_read_clear_intrbits()
761 		dw_readl(dev, DW_IC_CLR_ACTIVITY);  in i2c_dw_read_clear_intrbits()
763 		dw_readl(dev, DW_IC_CLR_STOP_DET);  in i2c_dw_read_clear_intrbits()
765 		dw_readl(dev, DW_IC_CLR_START_DET);  in i2c_dw_read_clear_intrbits()
767 		dw_readl(dev, DW_IC_CLR_GEN_CALL);  in i2c_dw_read_clear_intrbits()
781 	enabled = dw_readl(dev, DW_IC_ENABLE);  in i2c_dw_isr()
782 	stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);  in i2c_dw_isr()
818 		stat = dw_readl(dev, DW_IC_INTR_MASK);  in i2c_dw_isr()
833 	dw_readl(dev, DW_IC_CLR_INTR);  in i2c_dw_disable()
845 	return dw_readl(dev, DW_IC_COMP_PARAM_1);  in i2c_dw_read_comp_param()