Lines Matching refs:iface
36 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, in bfin_twi_handle_interrupt() argument
39 unsigned short mast_stat = read_MASTER_STAT(iface); in bfin_twi_handle_interrupt()
42 if (iface->writeNum <= 0) { in bfin_twi_handle_interrupt()
46 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) in bfin_twi_handle_interrupt()
47 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
48 read_MASTER_CTL(iface) | MDIR); in bfin_twi_handle_interrupt()
49 else if (iface->manual_stop) in bfin_twi_handle_interrupt()
50 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
51 read_MASTER_CTL(iface) | STOP); in bfin_twi_handle_interrupt()
52 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && in bfin_twi_handle_interrupt()
53 iface->cur_msg + 1 < iface->msg_num) { in bfin_twi_handle_interrupt()
54 if (iface->pmsg[iface->cur_msg + 1].flags & in bfin_twi_handle_interrupt()
56 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
57 read_MASTER_CTL(iface) | in bfin_twi_handle_interrupt()
60 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
61 read_MASTER_CTL(iface) & in bfin_twi_handle_interrupt()
66 while (iface->writeNum > 0 && in bfin_twi_handle_interrupt()
67 (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) { in bfin_twi_handle_interrupt()
68 write_XMT_DATA8(iface, *(iface->transPtr++)); in bfin_twi_handle_interrupt()
69 iface->writeNum--; in bfin_twi_handle_interrupt()
73 while (iface->readNum > 0 && in bfin_twi_handle_interrupt()
74 (read_FIFO_STAT(iface) & RCVSTAT)) { in bfin_twi_handle_interrupt()
76 *(iface->transPtr) = read_RCV_DATA8(iface); in bfin_twi_handle_interrupt()
77 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { in bfin_twi_handle_interrupt()
81 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; in bfin_twi_handle_interrupt()
85 if (iface->readNum == 1 && iface->manual_stop) in bfin_twi_handle_interrupt()
86 iface->readNum = *iface->transPtr + 1; in bfin_twi_handle_interrupt()
88 iface->transPtr++; in bfin_twi_handle_interrupt()
89 iface->readNum--; in bfin_twi_handle_interrupt()
92 if (iface->readNum == 0) { in bfin_twi_handle_interrupt()
93 if (iface->manual_stop) { in bfin_twi_handle_interrupt()
97 read_RCV_DATA16(iface); in bfin_twi_handle_interrupt()
98 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
99 read_MASTER_CTL(iface) | STOP); in bfin_twi_handle_interrupt()
100 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && in bfin_twi_handle_interrupt()
101 iface->cur_msg + 1 < iface->msg_num) { in bfin_twi_handle_interrupt()
102 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) in bfin_twi_handle_interrupt()
103 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
104 read_MASTER_CTL(iface) | MDIR); in bfin_twi_handle_interrupt()
106 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
107 read_MASTER_CTL(iface) & ~MDIR); in bfin_twi_handle_interrupt()
112 write_INT_MASK(iface, 0); in bfin_twi_handle_interrupt()
113 write_MASTER_STAT(iface, 0x3e); in bfin_twi_handle_interrupt()
114 write_MASTER_CTL(iface, 0); in bfin_twi_handle_interrupt()
115 iface->result = -EIO; in bfin_twi_handle_interrupt()
118 dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); in bfin_twi_handle_interrupt()
120 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); in bfin_twi_handle_interrupt()
122 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); in bfin_twi_handle_interrupt()
124 dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); in bfin_twi_handle_interrupt()
126 dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); in bfin_twi_handle_interrupt()
133 if (read_MASTER_STAT(iface) & SDASEN) { in bfin_twi_handle_interrupt()
136 write_MASTER_CTL(iface, SCLOVR); in bfin_twi_handle_interrupt()
138 write_MASTER_CTL(iface, 0); in bfin_twi_handle_interrupt()
140 } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--); in bfin_twi_handle_interrupt()
142 write_MASTER_CTL(iface, SDAOVR | SCLOVR); in bfin_twi_handle_interrupt()
144 write_MASTER_CTL(iface, SDAOVR); in bfin_twi_handle_interrupt()
146 write_MASTER_CTL(iface, 0); in bfin_twi_handle_interrupt()
152 if (iface->cur_mode == TWI_I2C_MODE_STANDARD && in bfin_twi_handle_interrupt()
153 iface->transPtr == NULL && in bfin_twi_handle_interrupt()
155 iface->result = 1; in bfin_twi_handle_interrupt()
157 complete(&iface->complete); in bfin_twi_handle_interrupt()
162 (read_MASTER_CTL(iface) & MEN) == 0 && in bfin_twi_handle_interrupt()
163 (iface->cur_mode == TWI_I2C_MODE_REPEAT || in bfin_twi_handle_interrupt()
164 iface->cur_mode == TWI_I2C_MODE_COMBINED)) { in bfin_twi_handle_interrupt()
165 iface->result = -1; in bfin_twi_handle_interrupt()
166 write_INT_MASK(iface, 0); in bfin_twi_handle_interrupt()
167 write_MASTER_CTL(iface, 0); in bfin_twi_handle_interrupt()
168 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { in bfin_twi_handle_interrupt()
169 if (iface->readNum == 0) { in bfin_twi_handle_interrupt()
173 iface->readNum = 1; in bfin_twi_handle_interrupt()
174 iface->manual_stop = 1; in bfin_twi_handle_interrupt()
175 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
176 read_MASTER_CTL(iface) | (0xff << 6)); in bfin_twi_handle_interrupt()
181 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
182 (read_MASTER_CTL(iface) & in bfin_twi_handle_interrupt()
184 (iface->readNum << 6)); in bfin_twi_handle_interrupt()
187 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
188 read_MASTER_CTL(iface) & ~RSTART); in bfin_twi_handle_interrupt()
189 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && in bfin_twi_handle_interrupt()
190 iface->cur_msg + 1 < iface->msg_num) { in bfin_twi_handle_interrupt()
191 iface->cur_msg++; in bfin_twi_handle_interrupt()
192 iface->transPtr = iface->pmsg[iface->cur_msg].buf; in bfin_twi_handle_interrupt()
193 iface->writeNum = iface->readNum = in bfin_twi_handle_interrupt()
194 iface->pmsg[iface->cur_msg].len; in bfin_twi_handle_interrupt()
196 write_MASTER_ADDR(iface, in bfin_twi_handle_interrupt()
197 iface->pmsg[iface->cur_msg].addr); in bfin_twi_handle_interrupt()
198 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) in bfin_twi_handle_interrupt()
199 iface->read_write = I2C_SMBUS_READ; in bfin_twi_handle_interrupt()
201 iface->read_write = I2C_SMBUS_WRITE; in bfin_twi_handle_interrupt()
203 if (iface->writeNum > 0) { in bfin_twi_handle_interrupt()
204 write_XMT_DATA8(iface, in bfin_twi_handle_interrupt()
205 *(iface->transPtr++)); in bfin_twi_handle_interrupt()
206 iface->writeNum--; in bfin_twi_handle_interrupt()
210 if (iface->pmsg[iface->cur_msg].len <= 255) { in bfin_twi_handle_interrupt()
211 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
212 (read_MASTER_CTL(iface) & in bfin_twi_handle_interrupt()
214 (iface->pmsg[iface->cur_msg].len << 6)); in bfin_twi_handle_interrupt()
215 iface->manual_stop = 0; in bfin_twi_handle_interrupt()
217 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
218 (read_MASTER_CTL(iface) | in bfin_twi_handle_interrupt()
220 iface->manual_stop = 1; in bfin_twi_handle_interrupt()
223 if (iface->cur_msg + 1 == iface->msg_num) in bfin_twi_handle_interrupt()
224 write_MASTER_CTL(iface, in bfin_twi_handle_interrupt()
225 read_MASTER_CTL(iface) & ~RSTART); in bfin_twi_handle_interrupt()
227 iface->result = 1; in bfin_twi_handle_interrupt()
228 write_INT_MASK(iface, 0); in bfin_twi_handle_interrupt()
229 write_MASTER_CTL(iface, 0); in bfin_twi_handle_interrupt()
231 complete(&iface->complete); in bfin_twi_handle_interrupt()
238 struct bfin_twi_iface *iface = dev_id; in bfin_twi_interrupt_entry() local
242 spin_lock_irqsave(&iface->lock, flags); in bfin_twi_interrupt_entry()
244 twi_int_status = read_INT_STAT(iface); in bfin_twi_interrupt_entry()
248 write_INT_STAT(iface, twi_int_status); in bfin_twi_interrupt_entry()
249 bfin_twi_handle_interrupt(iface, twi_int_status); in bfin_twi_interrupt_entry()
251 spin_unlock_irqrestore(&iface->lock, flags); in bfin_twi_interrupt_entry()
261 struct bfin_twi_iface *iface = adap->algo_data; in bfin_twi_do_master_xfer() local
265 if (!(read_CONTROL(iface) & TWI_ENA)) in bfin_twi_do_master_xfer()
268 if (read_MASTER_STAT(iface) & BUSBUSY) in bfin_twi_do_master_xfer()
271 iface->pmsg = msgs; in bfin_twi_do_master_xfer()
272 iface->msg_num = num; in bfin_twi_do_master_xfer()
273 iface->cur_msg = 0; in bfin_twi_do_master_xfer()
281 if (iface->msg_num > 1) in bfin_twi_do_master_xfer()
282 iface->cur_mode = TWI_I2C_MODE_REPEAT; in bfin_twi_do_master_xfer()
283 iface->manual_stop = 0; in bfin_twi_do_master_xfer()
284 iface->transPtr = pmsg->buf; in bfin_twi_do_master_xfer()
285 iface->writeNum = iface->readNum = pmsg->len; in bfin_twi_do_master_xfer()
286 iface->result = 0; in bfin_twi_do_master_xfer()
287 init_completion(&(iface->complete)); in bfin_twi_do_master_xfer()
289 write_MASTER_ADDR(iface, pmsg->addr); in bfin_twi_do_master_xfer()
294 write_FIFO_CTL(iface, 0x3); in bfin_twi_do_master_xfer()
295 write_FIFO_CTL(iface, 0); in bfin_twi_do_master_xfer()
298 iface->read_write = I2C_SMBUS_READ; in bfin_twi_do_master_xfer()
300 iface->read_write = I2C_SMBUS_WRITE; in bfin_twi_do_master_xfer()
302 if (iface->writeNum > 0) { in bfin_twi_do_master_xfer()
303 write_XMT_DATA8(iface, *(iface->transPtr++)); in bfin_twi_do_master_xfer()
304 iface->writeNum--; in bfin_twi_do_master_xfer()
309 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); in bfin_twi_do_master_xfer()
312 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); in bfin_twi_do_master_xfer()
315 write_MASTER_CTL(iface, pmsg->len << 6); in bfin_twi_do_master_xfer()
317 write_MASTER_CTL(iface, 0xff << 6); in bfin_twi_do_master_xfer()
318 iface->manual_stop = 1; in bfin_twi_do_master_xfer()
322 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | in bfin_twi_do_master_xfer()
323 (iface->msg_num > 1 ? RSTART : 0) | in bfin_twi_do_master_xfer()
324 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | in bfin_twi_do_master_xfer()
327 while (!iface->result) { in bfin_twi_do_master_xfer()
328 if (!wait_for_completion_timeout(&iface->complete, in bfin_twi_do_master_xfer()
330 iface->result = -1; in bfin_twi_do_master_xfer()
335 if (iface->result == 1) in bfin_twi_do_master_xfer()
336 rc = iface->cur_msg + 1; in bfin_twi_do_master_xfer()
338 rc = iface->result; in bfin_twi_do_master_xfer()
359 struct bfin_twi_iface *iface = adap->algo_data; in bfin_twi_do_smbus_xfer() local
362 if (!(read_CONTROL(iface) & TWI_ENA)) in bfin_twi_do_smbus_xfer()
365 if (read_MASTER_STAT(iface) & BUSBUSY) in bfin_twi_do_smbus_xfer()
368 iface->writeNum = 0; in bfin_twi_do_smbus_xfer()
369 iface->readNum = 0; in bfin_twi_do_smbus_xfer()
374 iface->transPtr = NULL; in bfin_twi_do_smbus_xfer()
375 iface->cur_mode = TWI_I2C_MODE_STANDARD; in bfin_twi_do_smbus_xfer()
379 iface->transPtr = NULL; in bfin_twi_do_smbus_xfer()
382 iface->readNum = 1; in bfin_twi_do_smbus_xfer()
384 iface->writeNum = 1; in bfin_twi_do_smbus_xfer()
385 iface->transPtr = &data->byte; in bfin_twi_do_smbus_xfer()
387 iface->cur_mode = TWI_I2C_MODE_STANDARD; in bfin_twi_do_smbus_xfer()
391 iface->readNum = 1; in bfin_twi_do_smbus_xfer()
392 iface->cur_mode = TWI_I2C_MODE_COMBINED; in bfin_twi_do_smbus_xfer()
394 iface->writeNum = 1; in bfin_twi_do_smbus_xfer()
395 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; in bfin_twi_do_smbus_xfer()
397 iface->transPtr = &data->byte; in bfin_twi_do_smbus_xfer()
401 iface->readNum = 2; in bfin_twi_do_smbus_xfer()
402 iface->cur_mode = TWI_I2C_MODE_COMBINED; in bfin_twi_do_smbus_xfer()
404 iface->writeNum = 2; in bfin_twi_do_smbus_xfer()
405 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; in bfin_twi_do_smbus_xfer()
407 iface->transPtr = (u8 *)&data->word; in bfin_twi_do_smbus_xfer()
410 iface->writeNum = 2; in bfin_twi_do_smbus_xfer()
411 iface->readNum = 2; in bfin_twi_do_smbus_xfer()
412 iface->cur_mode = TWI_I2C_MODE_COMBINED; in bfin_twi_do_smbus_xfer()
413 iface->transPtr = (u8 *)&data->word; in bfin_twi_do_smbus_xfer()
417 iface->readNum = 0; in bfin_twi_do_smbus_xfer()
418 iface->cur_mode = TWI_I2C_MODE_COMBINED; in bfin_twi_do_smbus_xfer()
420 iface->writeNum = data->block[0] + 1; in bfin_twi_do_smbus_xfer()
421 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; in bfin_twi_do_smbus_xfer()
423 iface->transPtr = data->block; in bfin_twi_do_smbus_xfer()
427 iface->readNum = data->block[0]; in bfin_twi_do_smbus_xfer()
428 iface->cur_mode = TWI_I2C_MODE_COMBINED; in bfin_twi_do_smbus_xfer()
430 iface->writeNum = data->block[0]; in bfin_twi_do_smbus_xfer()
431 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; in bfin_twi_do_smbus_xfer()
433 iface->transPtr = (u8 *)&data->block[1]; in bfin_twi_do_smbus_xfer()
439 iface->result = 0; in bfin_twi_do_smbus_xfer()
440 iface->manual_stop = 0; in bfin_twi_do_smbus_xfer()
441 iface->read_write = read_write; in bfin_twi_do_smbus_xfer()
442 iface->command = command; in bfin_twi_do_smbus_xfer()
443 init_completion(&(iface->complete)); in bfin_twi_do_smbus_xfer()
448 write_FIFO_CTL(iface, 0x3); in bfin_twi_do_smbus_xfer()
449 write_FIFO_CTL(iface, 0); in bfin_twi_do_smbus_xfer()
452 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); in bfin_twi_do_smbus_xfer()
455 write_MASTER_ADDR(iface, addr); in bfin_twi_do_smbus_xfer()
457 switch (iface->cur_mode) { in bfin_twi_do_smbus_xfer()
459 write_XMT_DATA8(iface, iface->command); in bfin_twi_do_smbus_xfer()
460 write_INT_MASK(iface, MCOMP | MERR | in bfin_twi_do_smbus_xfer()
461 ((iface->read_write == I2C_SMBUS_READ) ? in bfin_twi_do_smbus_xfer()
464 if (iface->writeNum + 1 <= 255) in bfin_twi_do_smbus_xfer()
465 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); in bfin_twi_do_smbus_xfer()
467 write_MASTER_CTL(iface, 0xff << 6); in bfin_twi_do_smbus_xfer()
468 iface->manual_stop = 1; in bfin_twi_do_smbus_xfer()
471 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | in bfin_twi_do_smbus_xfer()
475 write_XMT_DATA8(iface, iface->command); in bfin_twi_do_smbus_xfer()
476 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); in bfin_twi_do_smbus_xfer()
478 if (iface->writeNum > 0) in bfin_twi_do_smbus_xfer()
479 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); in bfin_twi_do_smbus_xfer()
481 write_MASTER_CTL(iface, 0x1 << 6); in bfin_twi_do_smbus_xfer()
483 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART | in bfin_twi_do_smbus_xfer()
487 write_MASTER_CTL(iface, 0); in bfin_twi_do_smbus_xfer()
492 if (iface->read_write != I2C_SMBUS_READ) { in bfin_twi_do_smbus_xfer()
493 if (iface->writeNum > 0) { in bfin_twi_do_smbus_xfer()
494 write_XMT_DATA8(iface, in bfin_twi_do_smbus_xfer()
495 *(iface->transPtr++)); in bfin_twi_do_smbus_xfer()
496 if (iface->writeNum <= 255) in bfin_twi_do_smbus_xfer()
497 write_MASTER_CTL(iface, in bfin_twi_do_smbus_xfer()
498 iface->writeNum << 6); in bfin_twi_do_smbus_xfer()
500 write_MASTER_CTL(iface, in bfin_twi_do_smbus_xfer()
502 iface->manual_stop = 1; in bfin_twi_do_smbus_xfer()
504 iface->writeNum--; in bfin_twi_do_smbus_xfer()
506 write_XMT_DATA8(iface, iface->command); in bfin_twi_do_smbus_xfer()
507 write_MASTER_CTL(iface, 1 << 6); in bfin_twi_do_smbus_xfer()
510 if (iface->readNum > 0 && iface->readNum <= 255) in bfin_twi_do_smbus_xfer()
511 write_MASTER_CTL(iface, in bfin_twi_do_smbus_xfer()
512 iface->readNum << 6); in bfin_twi_do_smbus_xfer()
513 else if (iface->readNum > 255) { in bfin_twi_do_smbus_xfer()
514 write_MASTER_CTL(iface, 0xff << 6); in bfin_twi_do_smbus_xfer()
515 iface->manual_stop = 1; in bfin_twi_do_smbus_xfer()
520 write_INT_MASK(iface, MCOMP | MERR | in bfin_twi_do_smbus_xfer()
521 ((iface->read_write == I2C_SMBUS_READ) ? in bfin_twi_do_smbus_xfer()
525 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | in bfin_twi_do_smbus_xfer()
526 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | in bfin_twi_do_smbus_xfer()
531 while (!iface->result) { in bfin_twi_do_smbus_xfer()
532 if (!wait_for_completion_timeout(&iface->complete, in bfin_twi_do_smbus_xfer()
534 iface->result = -1; in bfin_twi_do_smbus_xfer()
539 rc = (iface->result >= 0) ? 0 : -1; in bfin_twi_do_smbus_xfer()
575 struct bfin_twi_iface *iface = dev_get_drvdata(dev); in i2c_bfin_twi_suspend() local
577 iface->saved_clkdiv = read_CLKDIV(iface); in i2c_bfin_twi_suspend()
578 iface->saved_control = read_CONTROL(iface); in i2c_bfin_twi_suspend()
580 free_irq(iface->irq, iface); in i2c_bfin_twi_suspend()
583 write_CONTROL(iface, iface->saved_control & ~TWI_ENA); in i2c_bfin_twi_suspend()
590 struct bfin_twi_iface *iface = dev_get_drvdata(dev); in i2c_bfin_twi_resume() local
592 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, in i2c_bfin_twi_resume()
593 0, to_platform_device(dev)->name, iface); in i2c_bfin_twi_resume()
595 dev_err(dev, "Can't get IRQ %d !\n", iface->irq); in i2c_bfin_twi_resume()
600 write_CLKDIV(iface, iface->saved_clkdiv); in i2c_bfin_twi_resume()
603 write_CONTROL(iface, iface->saved_control); in i2c_bfin_twi_resume()
617 struct bfin_twi_iface *iface; in i2c_bfin_twi_probe() local
623 iface = devm_kzalloc(&pdev->dev, sizeof(struct bfin_twi_iface), in i2c_bfin_twi_probe()
625 if (!iface) { in i2c_bfin_twi_probe()
630 spin_lock_init(&(iface->lock)); in i2c_bfin_twi_probe()
634 iface->regs_base = devm_ioremap_resource(&pdev->dev, res); in i2c_bfin_twi_probe()
635 if (IS_ERR(iface->regs_base)) { in i2c_bfin_twi_probe()
637 return PTR_ERR(iface->regs_base); in i2c_bfin_twi_probe()
640 iface->irq = platform_get_irq(pdev, 0); in i2c_bfin_twi_probe()
641 if (iface->irq < 0) { in i2c_bfin_twi_probe()
646 p_adap = &iface->adap; in i2c_bfin_twi_probe()
650 p_adap->algo_data = iface; in i2c_bfin_twi_probe()
664 rc = devm_request_irq(&pdev->dev, iface->irq, bfin_twi_interrupt_entry, in i2c_bfin_twi_probe()
665 0, pdev->name, iface); in i2c_bfin_twi_probe()
667 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); in i2c_bfin_twi_probe()
673 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); in i2c_bfin_twi_probe()
682 write_CLKDIV(iface, (clkhilow << 8) | clkhilow); in i2c_bfin_twi_probe()
685 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); in i2c_bfin_twi_probe()
693 platform_set_drvdata(pdev, iface); in i2c_bfin_twi_probe()
696 "regs_base@%p\n", iface->regs_base); in i2c_bfin_twi_probe()
707 struct bfin_twi_iface *iface = platform_get_drvdata(pdev); in i2c_bfin_twi_remove() local
709 i2c_del_adapter(&(iface->adap)); in i2c_bfin_twi_remove()