Lines Matching refs:DC_WR_CH_CONF
53 #define DC_WR_CH_CONF 0x0 macro
227 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
232 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
263 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
265 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
274 reg = readl(dc->base + DC_WR_CH_CONF); in dc_irq_handler()
276 writel(reg, dc->base + DC_WR_CH_CONF); in dc_irq_handler()
306 val = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
308 writel(val, dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
436 priv->channels[1].base + DC_WR_CH_CONF); in ipu_dc_init()
438 priv->channels[5].base + DC_WR_CH_CONF); in ipu_dc_init()