Lines Matching refs:ipu
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) in ipu_cm_read() argument
40 return readl(ipu->cm_reg + offset); in ipu_cm_read()
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) in ipu_cm_write() argument
45 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
48 void ipu_srm_dp_sync_update(struct ipu_soc *ipu) in ipu_srm_dp_sync_update() argument
52 val = ipu_cm_read(ipu, IPU_SRM_PRI2); in ipu_srm_dp_sync_update()
54 ipu_cm_write(ipu, val, IPU_SRM_PRI2); in ipu_srm_dp_sync_update()
250 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
254 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
259 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
261 channel = &ipu->channel[num]; in ipu_idmac_get()
272 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
280 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put() local
282 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
284 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
288 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
307 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer() local
310 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); in __ipu_idmac_reset_current_buffer()
316 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer() local
320 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
322 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
327 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
331 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
361 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable() local
391 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
393 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
396 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
398 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
404 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) in ipu_module_enable() argument
409 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
411 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_enable()
418 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_enable()
420 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_enable()
422 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_enable()
424 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
430 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) in ipu_module_disable() argument
435 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
437 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_disable()
439 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_disable()
441 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_disable()
448 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_disable()
450 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
458 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer() local
461 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; in ipu_idmac_get_current_buffer()
467 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready() local
471 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
474 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
477 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
480 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
483 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
491 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer() local
495 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
499 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_select_buffer()
501 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_select_buffer()
503 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
509 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer() local
513 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
515 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ in ipu_idmac_clear_buffer()
518 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_clear_buffer()
521 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_clear_buffer()
524 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); in ipu_idmac_clear_buffer()
529 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_clear_buffer()
531 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
537 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel() local
541 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
543 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
545 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
547 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
553 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) in ipu_idmac_channel_busy() argument
555 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); in ipu_idmac_channel_busy()
561 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy() local
565 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
576 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms) in ipu_wait_interrupt() argument
581 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32)); in ipu_wait_interrupt()
582 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) { in ipu_wait_interrupt()
594 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel() local
598 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
601 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
603 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
608 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ in ipu_idmac_disable_channel()
610 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
612 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
616 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
618 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
622 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_disable_channel()
625 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
627 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
629 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
643 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark() local
647 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
649 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
654 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
656 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
660 static int ipu_memory_reset(struct ipu_soc *ipu) in ipu_memory_reset() argument
664 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); in ipu_memory_reset()
667 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { in ipu_memory_reset()
680 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) in ipu_set_csi_src_mux() argument
688 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
690 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_csi_src_mux()
695 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_csi_src_mux()
697 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
704 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) in ipu_set_ic_src_mux() argument
709 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
711 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_ic_src_mux()
721 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_ic_src_mux()
723 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
799 static int ipu_submodules_init(struct ipu_soc *ipu, in ipu_submodules_init() argument
806 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
808 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
814 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
821 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
828 ret = ipu_ic_init(ipu, dev, in ipu_submodules_init()
836 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
843 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
850 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
857 ret = ipu_dmfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
864 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
870 ret = ipu_smfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
880 ipu_dp_exit(ipu); in ipu_submodules_init()
882 ipu_dmfc_exit(ipu); in ipu_submodules_init()
884 ipu_dc_exit(ipu); in ipu_submodules_init()
886 ipu_di_exit(ipu, 1); in ipu_submodules_init()
888 ipu_di_exit(ipu, 0); in ipu_submodules_init()
890 ipu_ic_exit(ipu); in ipu_submodules_init()
892 ipu_csi_exit(ipu, 1); in ipu_submodules_init()
894 ipu_csi_exit(ipu, 0); in ipu_submodules_init()
896 ipu_cpmem_exit(ipu); in ipu_submodules_init()
902 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) in ipu_irq_handle() argument
909 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); in ipu_irq_handle()
910 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); in ipu_irq_handle()
913 irq = irq_linear_revmap(ipu->domain, in ipu_irq_handle()
923 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_irq_handler() local
929 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_irq_handler()
936 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_err_irq_handler() local
942 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_err_irq_handler()
947 int ipu_map_irq(struct ipu_soc *ipu, int irq) in ipu_map_irq() argument
951 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
953 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
959 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, in ipu_idmac_channel_irq() argument
962 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
966 static void ipu_submodules_exit(struct ipu_soc *ipu) in ipu_submodules_exit() argument
968 ipu_smfc_exit(ipu); in ipu_submodules_exit()
969 ipu_dp_exit(ipu); in ipu_submodules_exit()
970 ipu_dmfc_exit(ipu); in ipu_submodules_exit()
971 ipu_dc_exit(ipu); in ipu_submodules_exit()
972 ipu_di_exit(ipu, 1); in ipu_submodules_exit()
973 ipu_di_exit(ipu, 0); in ipu_submodules_exit()
974 ipu_ic_exit(ipu); in ipu_submodules_exit()
975 ipu_csi_exit(ipu, 1); in ipu_submodules_exit()
976 ipu_csi_exit(ipu, 0); in ipu_submodules_exit()
977 ipu_cpmem_exit(ipu); in ipu_submodules_exit()
1039 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) in ipu_add_client_devices() argument
1041 struct device *dev = ipu->dev; in ipu_add_client_devices()
1099 static int ipu_irq_init(struct ipu_soc *ipu) in ipu_irq_init() argument
1115 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1116 &irq_generic_chip_ops, ipu); in ipu_irq_init()
1117 if (!ipu->domain) { in ipu_irq_init()
1118 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1122 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1125 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1126 irq_domain_remove(ipu->domain); in ipu_irq_init()
1131 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); in ipu_irq_init()
1134 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1135 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1145 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); in ipu_irq_init()
1146 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, in ipu_irq_init()
1147 ipu); in ipu_irq_init()
1152 static void ipu_irq_exit(struct ipu_soc *ipu) in ipu_irq_exit() argument
1156 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); in ipu_irq_exit()
1157 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); in ipu_irq_exit()
1162 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1167 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1170 void ipu_dump(struct ipu_soc *ipu) in ipu_dump() argument
1174 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1175 ipu_cm_read(ipu, IPU_CONF)); in ipu_dump()
1176 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1177 ipu_idmac_read(ipu, IDMAC_CONF)); in ipu_dump()
1178 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1179 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); in ipu_dump()
1180 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1181 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); in ipu_dump()
1182 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1183 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); in ipu_dump()
1184 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1185 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); in ipu_dump()
1186 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1187 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); in ipu_dump()
1188 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1189 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); in ipu_dump()
1190 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1191 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1192 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1193 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
1194 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1195 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); in ipu_dump()
1196 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1197 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); in ipu_dump()
1198 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1199 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); in ipu_dump()
1200 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1201 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); in ipu_dump()
1203 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1204 ipu_cm_read(ipu, IPU_INT_CTRL(i))); in ipu_dump()
1212 struct ipu_soc *ipu; in ipu_probe() local
1232 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1233 if (!ipu) in ipu_probe()
1237 ipu->channel[i].ipu = ipu; in ipu_probe()
1238 ipu->devtype = devtype; in ipu_probe()
1239 ipu->ipu_type = devtype->type; in ipu_probe()
1241 spin_lock_init(&ipu->lock); in ipu_probe()
1242 mutex_init(&ipu->channel_lock); in ipu_probe()
1273 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1275 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1279 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1282 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1283 if (IS_ERR(ipu->clk)) { in ipu_probe()
1284 ret = PTR_ERR(ipu->clk); in ipu_probe()
1289 platform_set_drvdata(pdev, ipu); in ipu_probe()
1291 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1297 ipu->dev = &pdev->dev; in ipu_probe()
1298 ipu->irq_sync = irq_sync; in ipu_probe()
1299 ipu->irq_err = irq_err; in ipu_probe()
1301 ret = ipu_irq_init(ipu); in ipu_probe()
1310 ret = ipu_memory_reset(ipu); in ipu_probe()
1315 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), in ipu_probe()
1318 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1322 ret = ipu_add_client_devices(ipu, ipu_base); in ipu_probe()
1334 ipu_submodules_exit(ipu); in ipu_probe()
1337 ipu_irq_exit(ipu); in ipu_probe()
1339 clk_disable_unprepare(ipu->clk); in ipu_probe()
1345 struct ipu_soc *ipu = platform_get_drvdata(pdev); in ipu_remove() local
1348 ipu_submodules_exit(ipu); in ipu_remove()
1349 ipu_irq_exit(ipu); in ipu_remove()
1351 clk_disable_unprepare(ipu->clk); in ipu_remove()