144 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_cursor_set2()
235 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_cursor_move()
425 	struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);  in vmw_framebuffer_surface_dirty()
633 	struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);  in vmw_framebuffer_dmabuf_dirty()
698 	struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);  in vmw_framebuffer_pin()
731 	struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);  in vmw_framebuffer_unpin()
977 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_fb_create()
1193 int vmw_kms_write_svga(struct vmw_private *vmw_priv,  in vmw_kms_write_svga()  argument
1197 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_write_svga()
1198 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);  in vmw_kms_write_svga()
1199 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_write_svga()
1200 		vmw_mmio_write(pitch, vmw_priv->mmio_virt +  in vmw_kms_write_svga()
1202 	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);  in vmw_kms_write_svga()
1203 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);  in vmw_kms_write_svga()
1204 	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);  in vmw_kms_write_svga()
1206 	if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {  in vmw_kms_write_svga()
1208 			  depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));  in vmw_kms_write_svga()
1215 int vmw_kms_save_vga(struct vmw_private *vmw_priv)  in vmw_kms_save_vga()  argument
1220 	vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);  in vmw_kms_save_vga()
1221 	vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);  in vmw_kms_save_vga()
1222 	vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);  in vmw_kms_save_vga()
1223 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_save_vga()
1224 		vmw_priv->vga_pitchlock =  in vmw_kms_save_vga()
1225 		  vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);  in vmw_kms_save_vga()
1226 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_save_vga()
1227 		vmw_priv->vga_pitchlock = vmw_mmio_read(vmw_priv->mmio_virt +  in vmw_kms_save_vga()
1230 	if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))  in vmw_kms_save_vga()
1233 	vmw_priv->num_displays = vmw_read(vmw_priv,  in vmw_kms_save_vga()
1236 	if (vmw_priv->num_displays == 0)  in vmw_kms_save_vga()
1237 		vmw_priv->num_displays = 1;  in vmw_kms_save_vga()
1239 	for (i = 0; i < vmw_priv->num_displays; ++i) {  in vmw_kms_save_vga()
1240 		save = &vmw_priv->vga_save[i];  in vmw_kms_save_vga()
1241 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);  in vmw_kms_save_vga()
1242 		save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);  in vmw_kms_save_vga()
1243 		save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);  in vmw_kms_save_vga()
1244 		save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);  in vmw_kms_save_vga()
1245 		save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);  in vmw_kms_save_vga()
1246 		save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);  in vmw_kms_save_vga()
1247 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);  in vmw_kms_save_vga()
1248 		if (i == 0 && vmw_priv->num_displays == 1 &&  in vmw_kms_save_vga()
1256 			save->width = vmw_priv->vga_width - save->pos_x;  in vmw_kms_save_vga()
1257 			save->height = vmw_priv->vga_height - save->pos_y;  in vmw_kms_save_vga()
1264 int vmw_kms_restore_vga(struct vmw_private *vmw_priv)  in vmw_kms_restore_vga()  argument
1269 	vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);  in vmw_kms_restore_vga()
1270 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);  in vmw_kms_restore_vga()
1271 	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);  in vmw_kms_restore_vga()
1272 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_restore_vga()
1273 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,  in vmw_kms_restore_vga()
1274 			  vmw_priv->vga_pitchlock);  in vmw_kms_restore_vga()
1275 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_restore_vga()
1276 		vmw_mmio_write(vmw_priv->vga_pitchlock,  in vmw_kms_restore_vga()
1277 			       vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);  in vmw_kms_restore_vga()
1279 	if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))  in vmw_kms_restore_vga()
1282 	for (i = 0; i < vmw_priv->num_displays; ++i) {  in vmw_kms_restore_vga()
1283 		save = &vmw_priv->vga_save[i];  in vmw_kms_restore_vga()
1284 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);  in vmw_kms_restore_vga()
1285 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);  in vmw_kms_restore_vga()
1286 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);  in vmw_kms_restore_vga()
1287 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);  in vmw_kms_restore_vga()
1288 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);  in vmw_kms_restore_vga()
1289 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);  in vmw_kms_restore_vga()
1290 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);  in vmw_kms_restore_vga()
1388 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_gamma_set()
1418 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_du_connector_detect()
1532 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_du_connector_fill_modes()
1617 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_update_layout_ioctl()