37 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)  in vmw_fifo_have_3d()  argument
39 	u32 *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_have_3d()
41 	const struct vmw_fifo_state *fifo = &dev_priv->fifo;  in vmw_fifo_have_3d()
43 	if (!(dev_priv->capabilities & SVGA_CAP_3D))  in vmw_fifo_have_3d()
46 	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {  in vmw_fifo_have_3d()
49 		if (!dev_priv->has_mob)  in vmw_fifo_have_3d()
52 		spin_lock(&dev_priv->cap_lock);  in vmw_fifo_have_3d()
53 		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);  in vmw_fifo_have_3d()
54 		result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);  in vmw_fifo_have_3d()
55 		spin_unlock(&dev_priv->cap_lock);  in vmw_fifo_have_3d()
60 	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))  in vmw_fifo_have_3d()
80 	if (dev_priv->active_display_unit == vmw_du_legacy)  in vmw_fifo_have_3d()
86 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)  in vmw_fifo_have_pitchlock()  argument
88 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_have_pitchlock()
91 	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))  in vmw_fifo_have_pitchlock()
101 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)  in vmw_fifo_init()  argument
103 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_init()
120 	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));  in vmw_fifo_init()
121 	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));  in vmw_fifo_init()
122 	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));  in vmw_fifo_init()
124 	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);  in vmw_fifo_init()
125 	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);  in vmw_fifo_init()
126 	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);  in vmw_fifo_init()
128 	vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |  in vmw_fifo_init()
130 	vmw_write(dev_priv, SVGA_REG_TRACES, 0);  in vmw_fifo_init()
133 	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)  in vmw_fifo_init()
134 		min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);  in vmw_fifo_init()
141 	vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);  in vmw_fifo_init()
148 	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);  in vmw_fifo_init()
159 	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);  in vmw_fifo_init()
160 	vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);  in vmw_fifo_init()
166 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)  in vmw_fifo_ping_host()  argument
168 	u32 *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_ping_host()
172 		vmw_write(dev_priv, SVGA_REG_SYNC, reason);  in vmw_fifo_ping_host()
176 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)  in vmw_fifo_release()  argument
178 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_release()
180 	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);  in vmw_fifo_release()
181 	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)  in vmw_fifo_release()
184 	dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);  in vmw_fifo_release()
186 	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,  in vmw_fifo_release()
187 		  dev_priv->config_done_state);  in vmw_fifo_release()
188 	vmw_write(dev_priv, SVGA_REG_ENABLE,  in vmw_fifo_release()
189 		  dev_priv->enable_state);  in vmw_fifo_release()
190 	vmw_write(dev_priv, SVGA_REG_TRACES,  in vmw_fifo_release()
191 		  dev_priv->traces_state);  in vmw_fifo_release()
206 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)  in vmw_fifo_is_full()  argument
208 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_fifo_is_full()
217 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,  in vmw_fifo_wait_noirq()  argument
228 		prepare_to_wait(&dev_priv->fifo_queue, &__wait,  in vmw_fifo_wait_noirq()
231 		if (!vmw_fifo_is_full(dev_priv, bytes))  in vmw_fifo_wait_noirq()
244 	finish_wait(&dev_priv->fifo_queue, &__wait);  in vmw_fifo_wait_noirq()
245 	wake_up_all(&dev_priv->fifo_queue);  in vmw_fifo_wait_noirq()
250 static int vmw_fifo_wait(struct vmw_private *dev_priv,  in vmw_fifo_wait()  argument
256 	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))  in vmw_fifo_wait()
259 	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);  in vmw_fifo_wait()
260 	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))  in vmw_fifo_wait()
261 		return vmw_fifo_wait_noirq(dev_priv, bytes,  in vmw_fifo_wait()
264 	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,  in vmw_fifo_wait()
265 			       &dev_priv->fifo_queue_waiters);  in vmw_fifo_wait()
269 		    (dev_priv->fifo_queue,  in vmw_fifo_wait()
270 		     !vmw_fifo_is_full(dev_priv, bytes), timeout);  in vmw_fifo_wait()
273 		    (dev_priv->fifo_queue,  in vmw_fifo_wait()
274 		     !vmw_fifo_is_full(dev_priv, bytes), timeout);  in vmw_fifo_wait()
281 	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,  in vmw_fifo_wait()
282 				  &dev_priv->fifo_queue_waiters);  in vmw_fifo_wait()
297 static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,  in vmw_local_fifo_reserve()  argument
300 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;  in vmw_local_fifo_reserve()
301 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_local_fifo_reserve()
331 			else if (vmw_fifo_is_full(dev_priv, bytes)) {  in vmw_local_fifo_reserve()
332 				ret = vmw_fifo_wait(dev_priv, bytes,  in vmw_local_fifo_reserve()
344 				ret = vmw_fifo_wait(dev_priv, bytes,  in vmw_local_fifo_reserve()
382 void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,  in vmw_fifo_reserve_dx()  argument
387 	if (dev_priv->cman)  in vmw_fifo_reserve_dx()
388 		ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,  in vmw_fifo_reserve_dx()
391 		ret = vmw_local_fifo_reserve(dev_priv, bytes);  in vmw_fifo_reserve_dx()
447 static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)  in vmw_local_fifo_commit()  argument
449 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;  in vmw_local_fifo_commit()
450 	u32  *fifo_mem = dev_priv->mmio_virt;  in vmw_local_fifo_commit()
493 	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);  in vmw_local_fifo_commit()
497 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)  in vmw_fifo_commit()  argument
499 	if (dev_priv->cman)  in vmw_fifo_commit()
500 		vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);  in vmw_fifo_commit()
502 		vmw_local_fifo_commit(dev_priv, bytes);  in vmw_fifo_commit()
512 void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)  in vmw_fifo_commit_flush()  argument
514 	if (dev_priv->cman)  in vmw_fifo_commit_flush()
515 		vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);  in vmw_fifo_commit_flush()
517 		vmw_local_fifo_commit(dev_priv, bytes);  in vmw_fifo_commit_flush()
527 int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)  in vmw_fifo_flush()  argument
531 	if (dev_priv->cman)  in vmw_fifo_flush()
532 		return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);  in vmw_fifo_flush()
537 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)  in vmw_fifo_send_fence()  argument
539 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;  in vmw_fifo_send_fence()
545 	fm = vmw_fifo_reserve(dev_priv, bytes);  in vmw_fifo_send_fence()
547 		*seqno = atomic_read(&dev_priv->marker_seq);  in vmw_fifo_send_fence()
549 		(void)vmw_fallback_wait(dev_priv, false, true, *seqno,  in vmw_fifo_send_fence()
555 		*seqno = atomic_add_return(1, &dev_priv->marker_seq);  in vmw_fifo_send_fence()
565 		vmw_fifo_commit(dev_priv, 0);  in vmw_fifo_send_fence()
572 	vmw_fifo_commit_flush(dev_priv, bytes);  in vmw_fifo_send_fence()
574 	vmw_update_seqno(dev_priv, fifo_state);  in vmw_fifo_send_fence()
589 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,  in vmw_fifo_emit_dummy_legacy_query()  argument
598 	struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;  in vmw_fifo_emit_dummy_legacy_query()
604 	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));  in vmw_fifo_emit_dummy_legacy_query()
624 	vmw_fifo_commit(dev_priv, sizeof(*cmd));  in vmw_fifo_emit_dummy_legacy_query()
638 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,  in vmw_fifo_emit_dummy_gb_query()  argument
647 	struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;  in vmw_fifo_emit_dummy_gb_query()
653 	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));  in vmw_fifo_emit_dummy_gb_query()
668 	vmw_fifo_commit(dev_priv, sizeof(*cmd));  in vmw_fifo_emit_dummy_gb_query()
692 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,  in vmw_fifo_emit_dummy_query()  argument
695 	if (dev_priv->has_mob)  in vmw_fifo_emit_dummy_query()
696 		return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);  in vmw_fifo_emit_dummy_query()
698 	return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);  in vmw_fifo_emit_dummy_query()
701 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)  in vmw_fifo_reserve()  argument
703 	return vmw_fifo_reserve_dx(dev_priv, bytes, SVGA3D_INVALID_ID);  in vmw_fifo_reserve()