Lines Matching refs:BIT
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
68 # define V3D_INT_SPILLUSE BIT(3)
69 # define V3D_INT_OUTOMEM BIT(2)
70 # define V3D_INT_FLDONE BIT(1)
71 # define V3D_INT_FRDONE BIT(0)
76 # define V3D_CTRSTA BIT(15)
77 # define V3D_CTSEMA BIT(12)
78 # define V3D_CTRTSD BIT(8)
79 # define V3D_CTRUN BIT(5)
80 # define V3D_CTSUBS BIT(4)
81 # define V3D_CTERR BIT(3)
82 # define V3D_CTMODE BIT(0)
101 # define V3D_BMOOM BIT(8)
102 # define V3D_RMBUSY BIT(3)
103 # define V3D_RMACTIVE BIT(2)
104 # define V3D_BMBUSY BIT(1)
105 # define V3D_BMACTIVE BIT(0)
175 # define PV_CONTROL_CLR_AT_START BIT(14)
176 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
177 # define PV_CONTROL_WAIT_HSTART BIT(12)
182 # define PV_CONTROL_FIFO_CLR BIT(1)
183 # define PV_CONTROL_EN BIT(0)
186 # define PV_VCONTROL_INTERLACE BIT(4)
187 # define PV_VCONTROL_CONTINUOUS BIT(1)
188 # define PV_VCONTROL_VIDEN BIT(0)
221 # define PV_INT_VID_IDLE BIT(9)
222 # define PV_INT_VFP_END BIT(8)
223 # define PV_INT_VFP_START BIT(7)
224 # define PV_INT_VACT_START BIT(6)
225 # define PV_INT_VBP_START BIT(5)
226 # define PV_INT_VSYNC_START BIT(4)
227 # define PV_INT_HFP_START BIT(3)
228 # define PV_INT_HACT_START BIT(2)
229 # define PV_INT_HBP_START BIT(1)
230 # define PV_INT_HSYNC_START BIT(0)
238 # define SCALER_DISPCTRL_ENABLE BIT(31)
239 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
240 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
245 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13)
246 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12)
247 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11)
248 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10)
249 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9)
253 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8)
255 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7)
257 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
258 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
259 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
260 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3)
261 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2)
265 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1)
267 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
270 # define SCALER_DISPSTAT_COBLOW2 BIT(29)
271 # define SCALER_DISPSTAT_EOLN2 BIT(28)
272 # define SCALER_DISPSTAT_ESFRAME2 BIT(27)
273 # define SCALER_DISPSTAT_ESLINE2 BIT(26)
274 # define SCALER_DISPSTAT_EUFLOW2 BIT(25)
275 # define SCALER_DISPSTAT_EOF2 BIT(24)
277 # define SCALER_DISPSTAT_COBLOW1 BIT(21)
278 # define SCALER_DISPSTAT_EOLN1 BIT(20)
279 # define SCALER_DISPSTAT_ESFRAME1 BIT(19)
280 # define SCALER_DISPSTAT_ESLINE1 BIT(18)
281 # define SCALER_DISPSTAT_EUFLOW1 BIT(17)
282 # define SCALER_DISPSTAT_EOF1 BIT(16)
291 # define SCALER_DISPSTAT_COBLOW0 BIT(13)
293 # define SCALER_DISPSTAT_EOLN0 BIT(12)
297 # define SCALER_DISPSTAT_ESFRAME0 BIT(11)
301 # define SCALER_DISPSTAT_ESLINE0 BIT(10)
305 # define SCALER_DISPSTAT_EUFLOW0 BIT(9)
307 # define SCALER_DISPSTAT_EOF0 BIT(8)
310 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
312 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
314 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
318 # define SCALER_DISPSTAT_IRQDMA BIT(4)
319 # define SCALER_DISPSTAT_IRQDISP2 BIT(3)
320 # define SCALER_DISPSTAT_IRQDISP1 BIT(2)
324 # define SCALER_DISPSTAT_IRQDISP0 BIT(1)
326 # define SCALER_DISPSTAT_IRQSCL BIT(0)
345 # define SCALER_DISPCTRLX_ENABLE BIT(31)
346 # define SCALER_DISPCTRLX_RESET BIT(30)
361 # define SCALER_DISPSTATX_FULL BIT(29)
362 # define SCALER_DISPSTATX_EMPTY BIT(28)
386 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
387 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
392 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
395 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
398 # define VC4_HDMI_HORZA_VPOS BIT(14)
399 # define VC4_HDMI_HORZA_HPOS BIT(13)
416 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
417 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
418 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
419 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
420 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
421 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
422 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
423 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
424 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
425 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
429 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
430 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
431 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
432 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
433 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
459 # define VC4_HD_M_SW_RST BIT(2)
460 # define VC4_HD_M_ENABLE BIT(0)
465 # define VC4_HD_VID_CTL_ENABLE BIT(31)
466 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
467 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
468 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
469 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
480 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
486 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
487 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
527 #define SCALER_CTL0_END BIT(31)
528 #define SCALER_CTL0_VALID BIT(30)
533 #define SCALER_CTL0_HFLIP BIT(16)
534 #define SCALER_CTL0_VFLIP BIT(15)
540 #define SCALER_CTL0_UNITY BIT(4)