Lines Matching refs:value
222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
225 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
233 u32 value; in tegra_sor_dp_train_fast() local
237 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | in tegra_sor_dp_train_fast()
241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
243 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | in tegra_sor_dp_train_fast()
247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
249 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | in tegra_sor_dp_train_fast()
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
258 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
259 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_train_fast()
260 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_train_fast()
261 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ in tegra_sor_dp_train_fast()
262 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
264 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
265 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
267 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
271 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
272 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
274 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
280 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
284 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
287 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
295 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
296 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_train_fast()
297 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_train_fast()
298 value |= SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_dp_train_fast()
299 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
301 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
305 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
308 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
316 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
320 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
323 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
336 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
339 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
340 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
341 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
343 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
344 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
345 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
350 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
351 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
352 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
353 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
357 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
358 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
364 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
365 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
366 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
367 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
370 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
371 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
372 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
391 u32 value; in tegra_sor_setup_pwm() local
393 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
394 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
395 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
396 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
398 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
399 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
400 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
401 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
402 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
403 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
408 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
409 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
420 unsigned long value, timeout; in tegra_sor_attach() local
423 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
424 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
425 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
426 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
430 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
431 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
432 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
438 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
439 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
450 unsigned long value, timeout; in tegra_sor_wakeup() local
456 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
457 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
459 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
470 u32 value; in tegra_sor_power_up() local
472 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
473 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
474 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
479 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
480 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
666 unsigned long value, timeout; in tegra_sor_detach() local
669 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
670 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
671 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
677 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
678 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
682 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
686 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
687 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
688 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
692 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
693 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
694 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
700 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
701 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
707 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
715 unsigned long value, timeout; in tegra_sor_power_down() local
718 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
719 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
720 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
721 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
726 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
727 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
733 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
740 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_power_down()
741 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down()
743 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_power_down()
746 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down()
748 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
753 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
754 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down()
760 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down()
763 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
764 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
765 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
769 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_power_down()
770 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
771 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_power_down()
773 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
774 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
775 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
776 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
785 u32 value; in tegra_sor_crc_wait() local
790 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
791 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
807 u32 value; in tegra_sor_show_crc() local
816 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
817 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
818 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
820 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
821 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
822 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
824 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
825 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
826 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
833 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
835 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1102 u32 value; in tegra_sor_edp_disable() local
1120 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1121 value &= ~SOR_ENABLE; in tegra_sor_edp_disable()
1122 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1150 unsigned int *value)
1179 if (value) {
1181 *value = a + 1;
1183 *value = a;
1201 u32 value; in tegra_sor_edp_enable() local
1240 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1241 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_edp_enable()
1242 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_edp_enable()
1243 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1245 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1246 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1247 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1250 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_edp_enable()
1251 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_edp_enable()
1252 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_edp_enable()
1254 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | in tegra_sor_edp_enable()
1256 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1258 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1259 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_edp_enable()
1260 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1261 value |= SOR_PLL2_LVDS_ENABLE; in tegra_sor_edp_enable()
1262 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1264 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; in tegra_sor_edp_enable()
1265 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_edp_enable()
1268 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1269 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) in tegra_sor_edp_enable()
1275 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1276 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_edp_enable()
1277 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1278 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1285 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1286 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1287 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; in tegra_sor_edp_enable()
1288 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1291 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1292 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | in tegra_sor_edp_enable()
1294 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1296 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1297 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_edp_enable()
1298 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1300 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1301 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1302 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1312 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1313 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1314 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1319 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1320 value &= ~SOR_PLL0_VCOPD; in tegra_sor_edp_enable()
1321 value &= ~SOR_PLL0_PWR; in tegra_sor_edp_enable()
1322 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1324 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1325 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1326 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1331 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1332 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1333 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1341 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1344 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); in tegra_sor_edp_enable()
1346 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; in tegra_sor_edp_enable()
1349 value &= ~SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1351 value |= SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1354 value &= ~SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1356 value |= SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1358 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1360 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1361 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1362 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); in tegra_sor_edp_enable()
1363 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1366 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_edp_enable()
1368 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1371 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1372 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_edp_enable()
1379 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1380 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1381 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; in tegra_sor_edp_enable()
1382 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1385 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1386 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_edp_enable()
1388 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_edp_enable()
1389 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); in tegra_sor_edp_enable()
1391 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1392 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1394 for (i = 0, value = 0; i < 4; i++) { in tegra_sor_edp_enable()
1398 value = (value << 8) | lane; in tegra_sor_edp_enable()
1401 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1403 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1404 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_edp_enable()
1405 value |= SOR_DP_CONFIG_WATERMARK(config.watermark); in tegra_sor_edp_enable()
1407 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_edp_enable()
1408 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); in tegra_sor_edp_enable()
1410 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_edp_enable()
1411 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); in tegra_sor_edp_enable()
1414 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_edp_enable()
1416 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_edp_enable()
1418 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_edp_enable()
1419 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_edp_enable()
1420 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1422 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1423 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_edp_enable()
1424 value |= config.hblank_symbols & 0xffff; in tegra_sor_edp_enable()
1425 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1427 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1428 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_edp_enable()
1429 value |= config.vblank_symbols & 0xffff; in tegra_sor_edp_enable()
1430 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1433 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1434 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1435 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1458 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1459 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1460 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_edp_enable()
1461 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1463 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1464 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1465 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_edp_enable()
1468 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1470 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1478 value = (value << 8) | lane; in tegra_sor_edp_enable()
1481 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1500 value = SOR_STATE_ASY_PROTOCOL_DP_A | in tegra_sor_edp_enable()
1505 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_edp_enable()
1508 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_edp_enable()
1511 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_edp_enable()
1514 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_edp_enable()
1518 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_edp_enable()
1522 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_edp_enable()
1530 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1537 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_edp_enable()
1538 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_edp_enable()
1543 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_edp_enable()
1544 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_edp_enable()
1549 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_edp_enable()
1550 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_edp_enable()
1555 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_edp_enable()
1556 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_edp_enable()
1561 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_edp_enable()
1563 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1572 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1573 value |= SOR_ENABLE; in tegra_sor_edp_enable()
1574 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1619 u32 value = 0; in tegra_sor_hdmi_subpack() local
1623 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1625 return value; in tegra_sor_hdmi_subpack()
1634 u32 value; in tegra_sor_hdmi_write_infopack() local
1655 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1658 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1669 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1670 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1674 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1675 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1685 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1689 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1690 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1691 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1692 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1693 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1710 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1711 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1712 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1713 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1720 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
1722 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1723 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
1724 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1744 u32 value; in tegra_sor_hdmi_disable() local
1755 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
1756 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
1757 value &= ~SOR1_ENABLE; in tegra_sor_hdmi_disable()
1758 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
1785 u32 value; in tegra_sor_hdmi_enable() local
1811 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1812 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
1813 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1817 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
1818 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
1819 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1821 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1822 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
1823 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
1824 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1826 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1827 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
1828 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1832 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1833 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
1834 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
1835 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1840 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
1842 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1845 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1846 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
1852 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
1854 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1857 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1858 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
1864 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1865 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
1866 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
1869 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
1871 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
1873 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1876 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1877 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
1878 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
1879 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
1880 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1882 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
1884 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
1886 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
1888 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
1889 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
1892 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
1893 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
1896 value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) | in tegra_sor_hdmi_enable()
1906 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
1914 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
1918 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
1920 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
1924 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
1926 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
1932 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
1934 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
1936 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
1937 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
1939 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
1940 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
1941 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
1953 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
1954 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
1955 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
1958 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1959 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
1960 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1970 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1971 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
1972 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
1973 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
1974 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
1975 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1979 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_hdmi_enable()
1980 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
1981 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
1982 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_hdmi_enable()
1984 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
1985 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
1986 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); in tegra_sor_hdmi_enable()
1987 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1989 value = settings->drive_current[0] << 24 | in tegra_sor_hdmi_enable()
1993 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
1995 value = settings->preemphasis[0] << 24 | in tegra_sor_hdmi_enable()
1999 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2001 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2002 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2003 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2004 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); in tegra_sor_hdmi_enable()
2005 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2008 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2009 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2010 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2013 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2014 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2016 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2017 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2018 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2022 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2026 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2034 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2041 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2042 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_hdmi_enable()
2043 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_hdmi_enable()
2044 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2046 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_hdmi_enable()
2050 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_hdmi_enable()
2053 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_hdmi_enable()
2056 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_hdmi_enable()
2059 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_hdmi_enable()
2063 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_hdmi_enable()
2067 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_hdmi_enable()
2075 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2077 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2078 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2079 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2080 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2082 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2083 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2084 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2085 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2092 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_hdmi_enable()
2093 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_hdmi_enable()
2099 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_hdmi_enable()
2100 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_hdmi_enable()
2106 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_hdmi_enable()
2107 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_hdmi_enable()
2113 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_hdmi_enable()
2114 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_hdmi_enable()
2125 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2126 value |= SOR1_ENABLE | SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2127 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()