Lines Matching refs:tegra_sor_writel
222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() function
241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
256 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_train_fast()
262 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
267 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
274 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
287 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
299 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
308 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
323 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
341 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
345 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
353 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
367 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
372 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
377 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
378 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
379 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
384 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
385 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
386 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
396 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
403 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
426 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
432 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
474 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
671 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
688 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
694 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
721 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
743 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_power_down()
748 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
765 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
771 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_power_down()
776 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
818 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
822 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
826 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
832 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1112 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_edp_disable()
1243 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1247 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1252 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_edp_enable()
1256 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1262 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1265 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_edp_enable()
1278 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1288 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1294 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1298 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1302 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1314 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1322 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1326 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1333 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1358 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1363 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1368 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1382 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1392 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1401 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1420 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1425 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1430 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1435 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1461 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1470 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1481 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1530 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1538 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_edp_enable()
1544 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_edp_enable()
1550 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_edp_enable()
1556 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_edp_enable()
1558 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); in tegra_sor_edp_enable()
1563 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1658 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1670 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1675 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1693 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1713 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1724 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1751 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
1813 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1819 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1824 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1828 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1835 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1842 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1854 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1880 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1884 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
1888 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
1889 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
1893 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
1906 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
1908 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
1920 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
1926 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
1955 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
1960 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1975 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1982 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_hdmi_enable()
1987 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1993 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
1999 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2005 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2010 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2075 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2080 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2085 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2093 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_hdmi_enable()
2100 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_hdmi_enable()
2107 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_hdmi_enable()
2114 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_hdmi_enable()
2116 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); in tegra_sor_hdmi_enable()