Lines Matching refs:tegra_sor_readl
217 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) in tegra_sor_readl() function
258 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
264 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
271 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
295 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
339 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
343 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
350 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
357 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
364 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
370 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
393 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
398 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
408 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
423 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
430 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
438 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
456 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
472 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
479 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
669 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
677 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
686 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
692 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
700 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
718 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
726 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
740 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_power_down()
753 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
763 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
769 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_power_down()
773 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
790 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
816 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
820 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
824 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
833 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
859 tegra_sor_readl(sor, name)) in tegra_sor_show_regs()
1240 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1245 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1250 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_edp_enable()
1258 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1268 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1275 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1285 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1291 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1296 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1300 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1312 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1319 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1324 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1331 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1341 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1360 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1371 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1379 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1385 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1403 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1422 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1427 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1433 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1458 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1463 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1689 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1710 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1722 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1811 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1817 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
1821 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1826 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1832 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1845 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1857 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1864 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1876 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
1958 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1970 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1979 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_hdmi_enable()
1984 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
2001 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2008 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2041 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2077 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2082 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()