1100 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);  in tegra_sor_edp_disable()  local
1119 	if (dc) {  in tegra_sor_edp_disable()
1120 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_edp_disable()
1122 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_edp_disable()
1124 		tegra_dc_commit(dc);  in tegra_sor_edp_disable()
1194 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);  in tegra_sor_edp_enable()  local
1502 		SOR_STATE_ASY_OWNER(dc->pipe + 1);  in tegra_sor_edp_enable()
1538 	tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));  in tegra_sor_edp_enable()
1544 	tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));  in tegra_sor_edp_enable()
1550 	tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));  in tegra_sor_edp_enable()
1556 	tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));  in tegra_sor_edp_enable()
1558 	tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));  in tegra_sor_edp_enable()
1572 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_edp_enable()
1574 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_edp_enable()
1576 	tegra_dc_commit(dc);  in tegra_sor_edp_enable()
1596 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);  in tegra_sor_encoder_atomic_check()  local
1601 	err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,  in tegra_sor_encoder_atomic_check()
1742 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);  in tegra_sor_hdmi_disable()  local
1755 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_hdmi_disable()
1758 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_hdmi_disable()
1760 	tegra_dc_commit(dc);  in tegra_sor_hdmi_disable()
1779 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);  in tegra_sor_hdmi_enable()  local
1914 	value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);  in tegra_sor_hdmi_enable()
1934 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);  in tegra_sor_hdmi_enable()
1937 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);  in tegra_sor_hdmi_enable()
1939 	value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);  in tegra_sor_hdmi_enable()
1941 	tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);  in tegra_sor_hdmi_enable()
2014 	tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);  in tegra_sor_hdmi_enable()
2016 	value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);  in tegra_sor_hdmi_enable()
2034 	tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);  in tegra_sor_hdmi_enable()
2047 		 SOR_STATE_ASY_OWNER(dc->pipe + 1);  in tegra_sor_hdmi_enable()
2077 	value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));  in tegra_sor_hdmi_enable()
2080 	tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));  in tegra_sor_hdmi_enable()
2082 	value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));  in tegra_sor_hdmi_enable()
2085 	tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));  in tegra_sor_hdmi_enable()
2093 	tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));  in tegra_sor_hdmi_enable()
2100 	tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));  in tegra_sor_hdmi_enable()
2107 	tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));  in tegra_sor_hdmi_enable()
2114 	tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));  in tegra_sor_hdmi_enable()
2116 	tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));  in tegra_sor_hdmi_enable()
2125 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_hdmi_enable()
2127 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_sor_hdmi_enable()
2129 	tegra_dc_commit(dc);  in tegra_sor_hdmi_enable()