98 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,  in tegra_hdmi_writel()  argument
101 	writel(value, hdmi->regs + (offset << 2));  in tegra_hdmi_writel()
463 		u32 value;  in tegra_hdmi_setup_audio_fs_tables()  local
473 		value = AUDIO_FS_LOW(eight_half - delta) |  in tegra_hdmi_setup_audio_fs_tables()
475 		tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));  in tegra_hdmi_setup_audio_fs_tables()
484 	u32 value;  in tegra_hdmi_setup_audio()  local
488 		value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;  in tegra_hdmi_setup_audio()
492 		value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;  in tegra_hdmi_setup_audio()
496 		value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;  in tegra_hdmi_setup_audio()
501 		value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |  in tegra_hdmi_setup_audio()
503 		tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);  in tegra_hdmi_setup_audio()
505 		value |= AUDIO_CNTRL0_INJECT_NULLSMPL;  in tegra_hdmi_setup_audio()
506 		tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);  in tegra_hdmi_setup_audio()
508 		value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |  in tegra_hdmi_setup_audio()
510 		tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);  in tegra_hdmi_setup_audio()
522 	value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |  in tegra_hdmi_setup_audio()
524 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);  in tegra_hdmi_setup_audio()
529 	value = ACR_SUBPACK_CTS(config->cts);  in tegra_hdmi_setup_audio()
530 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);  in tegra_hdmi_setup_audio()
532 	value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);  in tegra_hdmi_setup_audio()
533 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);  in tegra_hdmi_setup_audio()
535 	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);  in tegra_hdmi_setup_audio()
536 	value &= ~AUDIO_N_RESETF;  in tegra_hdmi_setup_audio()
537 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);  in tegra_hdmi_setup_audio()
580 	u32 value = 0;  in tegra_hdmi_subpack()  local
584 		value = (value << 8) | ptr[i - 1];  in tegra_hdmi_subpack()
586 	return value;  in tegra_hdmi_subpack()
595 	u32 value;  in tegra_hdmi_write_infopack()  local
616 	value = INFOFRAME_HEADER_TYPE(ptr[0]) |  in tegra_hdmi_write_infopack()
619 	tegra_hdmi_writel(hdmi, value, offset);  in tegra_hdmi_write_infopack()
630 		value = tegra_hdmi_subpack(&ptr[i], num);  in tegra_hdmi_write_infopack()
631 		tegra_hdmi_writel(hdmi, value, offset++);  in tegra_hdmi_write_infopack()
635 		value = tegra_hdmi_subpack(&ptr[i + 4], num);  in tegra_hdmi_write_infopack()
636 		tegra_hdmi_writel(hdmi, value, offset++);  in tegra_hdmi_write_infopack()
716 	u32 value;  in tegra_hdmi_setup_stereo_infoframe()  local
719 		value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);  in tegra_hdmi_setup_stereo_infoframe()
720 		value &= ~GENERIC_CTRL_ENABLE;  in tegra_hdmi_setup_stereo_infoframe()
721 		tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);  in tegra_hdmi_setup_stereo_infoframe()
737 	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);  in tegra_hdmi_setup_stereo_infoframe()
738 	value |= GENERIC_CTRL_ENABLE;  in tegra_hdmi_setup_stereo_infoframe()
739 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);  in tegra_hdmi_setup_stereo_infoframe()
745 	u32 value;  in tegra_hdmi_setup_tmds()  local
754 	value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);  in tegra_hdmi_setup_tmds()
755 	value |= hdmi->config->fuse_override_value;  in tegra_hdmi_setup_tmds()
756 	tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);  in tegra_hdmi_setup_tmds()
819 	u32 value;  in tegra_hdmi_encoder_disable()  local
826 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_hdmi_encoder_disable()
827 		value &= ~HDMI_ENABLE;  in tegra_hdmi_encoder_disable()
828 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_hdmi_encoder_disable()
844 	u32 value;  in tegra_hdmi_encoder_enable()  local
863 	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);  in tegra_hdmi_encoder_enable()
864 	value &= ~SOR_PLL_PDBG;  in tegra_hdmi_encoder_enable()
865 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);  in tegra_hdmi_encoder_enable()
869 	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);  in tegra_hdmi_encoder_enable()
870 	value &= ~SOR_PLL_PWR;  in tegra_hdmi_encoder_enable()
871 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);  in tegra_hdmi_encoder_enable()
883 	value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |  in tegra_hdmi_encoder_enable()
885 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);  in tegra_hdmi_encoder_enable()
887 	value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);  in tegra_hdmi_encoder_enable()
888 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);  in tegra_hdmi_encoder_enable()
890 	value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |  in tegra_hdmi_encoder_enable()
892 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);  in tegra_hdmi_encoder_enable()
895 		value = HDMI_SRC_DISPLAYB;  in tegra_hdmi_encoder_enable()
897 		value = HDMI_SRC_DISPLAYA;  in tegra_hdmi_encoder_enable()
902 				  value | ARM_VIDEO_RANGE_FULL,  in tegra_hdmi_encoder_enable()
906 				  value | ARM_VIDEO_RANGE_LIMITED,  in tegra_hdmi_encoder_enable()
910 	value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);  in tegra_hdmi_encoder_enable()
911 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);  in tegra_hdmi_encoder_enable()
926 	value = HDMI_CTRL_REKEY(rekey);  in tegra_hdmi_encoder_enable()
927 	value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +  in tegra_hdmi_encoder_enable()
931 		value |= HDMI_CTRL_ENABLE;  in tegra_hdmi_encoder_enable()
933 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);  in tegra_hdmi_encoder_enable()
961 	value = SOR_SEQ_INST_WAIT_TIME(1) |  in tegra_hdmi_encoder_enable()
968 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));  in tegra_hdmi_encoder_enable()
969 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));  in tegra_hdmi_encoder_enable()
971 	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);  in tegra_hdmi_encoder_enable()
972 	value &= ~SOR_CSTM_ROTCLK(~0);  in tegra_hdmi_encoder_enable()
973 	value |= SOR_CSTM_ROTCLK(2);  in tegra_hdmi_encoder_enable()
974 	value |= SOR_CSTM_PLLDIV;  in tegra_hdmi_encoder_enable()
975 	value &= ~SOR_CSTM_LVDS_ENABLE;  in tegra_hdmi_encoder_enable()
976 	value &= ~SOR_CSTM_MODE_MASK;  in tegra_hdmi_encoder_enable()
977 	value |= SOR_CSTM_MODE_TMDS;  in tegra_hdmi_encoder_enable()
978 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);  in tegra_hdmi_encoder_enable()
996 		value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);  in tegra_hdmi_encoder_enable()
997 	} while (value & SOR_PWR_SETTING_NEW_PENDING);  in tegra_hdmi_encoder_enable()
999 	value = SOR_STATE_ASY_CRCMODE_COMPLETE |  in tegra_hdmi_encoder_enable()
1007 		value |= SOR_STATE_ASY_HSYNCPOL_POS;  in tegra_hdmi_encoder_enable()
1010 		value |= SOR_STATE_ASY_HSYNCPOL_NEG;  in tegra_hdmi_encoder_enable()
1013 		value |= SOR_STATE_ASY_VSYNCPOL_POS;  in tegra_hdmi_encoder_enable()
1016 		value |= SOR_STATE_ASY_VSYNCPOL_NEG;  in tegra_hdmi_encoder_enable()
1018 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);  in tegra_hdmi_encoder_enable()
1020 	value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;  in tegra_hdmi_encoder_enable()
1021 	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);  in tegra_hdmi_encoder_enable()
1025 	tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,  in tegra_hdmi_encoder_enable()
1029 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_hdmi_encoder_enable()
1030 	value |= HDMI_ENABLE;  in tegra_hdmi_encoder_enable()
1031 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_hdmi_encoder_enable()