112 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,  in tegra_dsi_writel()  argument
115 	writel(value, dsi->regs + (reg << 2));  in tegra_dsi_writel()
381 	u32 value;  in tegra_dsi_set_phy_timing()  local
383 	value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |  in tegra_dsi_set_phy_timing()
387 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);  in tegra_dsi_set_phy_timing()
389 	value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |  in tegra_dsi_set_phy_timing()
393 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);  in tegra_dsi_set_phy_timing()
395 	value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |  in tegra_dsi_set_phy_timing()
398 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);  in tegra_dsi_set_phy_timing()
400 	value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |  in tegra_dsi_set_phy_timing()
403 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);  in tegra_dsi_set_phy_timing()
466 	u32 value;  in tegra_dsi_ganged_enable()  local
471 	value = DSI_GANGED_MODE_CONTROL_ENABLE;  in tegra_dsi_ganged_enable()
472 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_enable()
477 	u32 value;  in tegra_dsi_enable()  local
479 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_enable()
480 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_enable()
481 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_enable()
504 	u32 value;  in tegra_dsi_configure()  local
526 	value = DSI_CONTROL_CHANNEL(0) |  in tegra_dsi_configure()
530 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
534 	value = DSI_HOST_CONTROL_HS;  in tegra_dsi_configure()
535 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_configure()
537 	value = tegra_dsi_readl(dsi, DSI_CONTROL);  in tegra_dsi_configure()
540 		value |= DSI_CONTROL_HS_CLK_CTRL;  in tegra_dsi_configure()
542 	value &= ~DSI_CONTROL_TX_TRIG(3);  in tegra_dsi_configure()
546 		value &= ~DSI_CONTROL_DCS_ENABLE;  in tegra_dsi_configure()
548 		value |= DSI_CONTROL_DCS_ENABLE;  in tegra_dsi_configure()
550 	value |= DSI_CONTROL_VIDEO_ENABLE;  in tegra_dsi_configure()
551 	value &= ~DSI_CONTROL_HOST_ENABLE;  in tegra_dsi_configure()
552 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
605 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |  in tegra_dsi_configure()
607 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);  in tegra_dsi_configure()
622 			value = bclk - bclk_ganged + delay + 20;  in tegra_dsi_configure()
625 			value = 8 * mul / div;  in tegra_dsi_configure()
628 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);  in tegra_dsi_configure()
646 	u32 value;  in tegra_dsi_wait_idle()  local
651 		value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_wait_idle()
652 		if (value & DSI_STATUS_IDLE)  in tegra_dsi_wait_idle()
663 	u32 value;  in tegra_dsi_video_disable()  local
665 	value = tegra_dsi_readl(dsi, DSI_CONTROL);  in tegra_dsi_video_disable()
666 	value &= ~DSI_CONTROL_VIDEO_ENABLE;  in tegra_dsi_video_disable()
667 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_video_disable()
684 	u32 value;  in tegra_dsi_set_timeout()  local
688 	value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);  in tegra_dsi_set_timeout()
689 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);  in tegra_dsi_set_timeout()
693 	value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);  in tegra_dsi_set_timeout()
694 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);  in tegra_dsi_set_timeout()
696 	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);  in tegra_dsi_set_timeout()
697 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);  in tegra_dsi_set_timeout()
705 	u32 value;  in tegra_dsi_disable()  local
712 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_disable()
713 	value &= ~DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_disable()
714 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_disable()
724 	u32 value;  in tegra_dsi_soft_reset()  local
726 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
727 	value &= ~DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_soft_reset()
728 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
732 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
733 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_soft_reset()
734 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
738 	value = tegra_dsi_readl(dsi, DSI_TRIGGER);  in tegra_dsi_soft_reset()
739 	if (value)  in tegra_dsi_soft_reset()
803 	u32 value;  in tegra_dsi_encoder_disable()  local
816 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_disable()
817 		value &= ~DSI_ENABLE;  in tegra_dsi_encoder_disable()
818 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_disable()
844 	u32 value;  in tegra_dsi_encoder_enable()  local
862 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_enable()
863 	value |= DSI_ENABLE;  in tegra_dsi_encoder_enable()
864 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_enable()
966 	u32 value;  in tegra_dsi_pad_enable()  local
968 	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);  in tegra_dsi_pad_enable()
969 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_enable()
976 	u32 value;  in tegra_dsi_pad_calibrate()  local
987 	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |  in tegra_dsi_pad_calibrate()
990 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
992 	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |  in tegra_dsi_pad_calibrate()
994 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);  in tegra_dsi_pad_calibrate()
1120 	u32 value;  in tegra_dsi_read_response()  local
1123 	value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_read_response()
1125 	switch (value & 0x3f) {  in tegra_dsi_read_response()
1127 		errors = (value >> 8) & 0xffff;  in tegra_dsi_read_response()
1137 		rx[0] = (value >> 8) & 0xff;  in tegra_dsi_read_response()
1142 		rx[0] = (value >>  8) & 0xff;  in tegra_dsi_read_response()
1143 		rx[1] = (value >> 16) & 0xff;  in tegra_dsi_read_response()
1148 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);  in tegra_dsi_read_response()
1152 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);  in tegra_dsi_read_response()
1157 			value & 0x3f);  in tegra_dsi_read_response()
1167 			value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_read_response()
1170 				rx[j + k] = (value >> (k << 3)) & 0xff;  in tegra_dsi_read_response()
1184 		u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);  in tegra_dsi_transmit()  local
1185 		if ((value & DSI_TRIGGER_HOST) == 0)  in tegra_dsi_transmit()
1201 		u32 value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_wait_for_response()  local
1202 		u8 count = value & 0x1f;  in tegra_dsi_wait_for_response()
1219 	u32 value;  in tegra_dsi_writesl()  local
1222 		value = 0;  in tegra_dsi_writesl()
1225 			value |= buf[j + i] << (i << 3);  in tegra_dsi_writesl()
1227 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_writesl()
1239 	u32 value;  in tegra_dsi_host_transfer()  local
1252 	value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_host_transfer()
1253 	if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {  in tegra_dsi_host_transfer()
1254 		value = DSI_HOST_CONTROL_FIFO_RESET;  in tegra_dsi_host_transfer()
1255 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1259 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1260 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_host_transfer()
1261 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1265 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |  in tegra_dsi_host_transfer()
1269 		value |= DSI_HOST_CONTROL_HS;  in tegra_dsi_host_transfer()
1276 		value |= DSI_HOST_CONTROL_FIFO_SEL;  in tegra_dsi_host_transfer()
1278 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1286 		value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1287 		value |= DSI_HOST_CONTROL_PKT_BTA;  in tegra_dsi_host_transfer()
1288 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1291 	value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;  in tegra_dsi_host_transfer()
1292 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_host_transfer()
1295 	value = header[2] << 16 | header[1] << 8 | header[0];  in tegra_dsi_host_transfer()
1296 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_host_transfer()
1315 		value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_host_transfer()
1316 		switch (value) {  in tegra_dsi_host_transfer()
1330 			dev_err(dsi->dev, "unknown status: %08x\n", value);  in tegra_dsi_host_transfer()