112 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,  in tegra_dsi_writel()  function
387 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);  in tegra_dsi_set_phy_timing()
393 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);  in tegra_dsi_set_phy_timing()
398 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);  in tegra_dsi_set_phy_timing()
403 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);  in tegra_dsi_set_phy_timing()
468 	tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);  in tegra_dsi_ganged_enable()
469 	tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);  in tegra_dsi_ganged_enable()
472 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_enable()
481 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_enable()
530 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
532 	tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);  in tegra_dsi_configure()
535 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_configure()
552 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
555 		tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);  in tegra_dsi_configure()
578 		tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);  in tegra_dsi_configure()
579 		tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);  in tegra_dsi_configure()
580 		tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);  in tegra_dsi_configure()
581 		tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);  in tegra_dsi_configure()
584 		tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);  in tegra_dsi_configure()
600 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);  in tegra_dsi_configure()
601 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);  in tegra_dsi_configure()
602 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);  in tegra_dsi_configure()
603 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);  in tegra_dsi_configure()
607 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);  in tegra_dsi_configure()
628 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);  in tegra_dsi_configure()
667 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_video_disable()
675 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);  in tegra_dsi_ganged_disable()
676 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);  in tegra_dsi_ganged_disable()
677 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_disable()
689 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);  in tegra_dsi_set_timeout()
694 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);  in tegra_dsi_set_timeout()
697 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);  in tegra_dsi_set_timeout()
714 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_disable()
728 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
734 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
740 		tegra_dsi_writel(dsi, 0, DSI_TRIGGER);  in tegra_dsi_soft_reset()
969 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_enable()
978 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_calibrate()
979 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);  in tegra_dsi_pad_calibrate()
980 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
981 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);  in tegra_dsi_pad_calibrate()
982 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);  in tegra_dsi_pad_calibrate()
990 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
994 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);  in tegra_dsi_pad_calibrate()
1179 	tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);  in tegra_dsi_transmit()
1227 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_writesl()
1255 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1261 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1278 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1288 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1292 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_host_transfer()
1296 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_host_transfer()