Lines Matching refs:mul
43 unsigned int mul; member
501 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
512 mul = state->mul; in tegra_dsi_configure()
559 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
562 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
565 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
571 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
584 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
594 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
597 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
616 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
620 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
625 value = 8 * mul / div; in tegra_dsi_configure()
892 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); in tegra_dsi_encoder_atomic_check()
905 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); in tegra_dsi_encoder_atomic_check()
907 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, in tegra_dsi_encoder_atomic_check()
946 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; in tegra_dsi_encoder_atomic_check()