66 				      u32 value, unsigned long offset)  in tegra_dpaux_writel()  argument
68 	writel(value, dpaux->regs + (offset << 2));  in tegra_dpaux_writel()
78 		u32 value = 0;  in tegra_dpaux_write_fifo()  local
81 			value |= buffer[i * 4 + j] << (j * 8);  in tegra_dpaux_write_fifo()
83 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));  in tegra_dpaux_write_fifo()
94 		u32 value;  in tegra_dpaux_read_fifo()  local
96 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));  in tegra_dpaux_read_fifo()
99 			buffer[i * 4 + j] = value >> (j * 8);  in tegra_dpaux_read_fifo()
110 	u32 value;  in tegra_dpaux_transfer()  local
125 			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;  in tegra_dpaux_transfer()
133 		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);  in tegra_dpaux_transfer()
139 			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;  in tegra_dpaux_transfer()
141 			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;  in tegra_dpaux_transfer()
147 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;  in tegra_dpaux_transfer()
149 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;  in tegra_dpaux_transfer()
155 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;  in tegra_dpaux_transfer()
157 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;  in tegra_dpaux_transfer()
162 		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;  in tegra_dpaux_transfer()
166 		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;  in tegra_dpaux_transfer()
174 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
182 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
183 	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;  in tegra_dpaux_transfer()
184 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
191 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
194 	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)  in tegra_dpaux_transfer()
197 	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||  in tegra_dpaux_transfer()
198 	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||  in tegra_dpaux_transfer()
199 	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))  in tegra_dpaux_transfer()
202 	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {  in tegra_dpaux_transfer()
226 			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;  in tegra_dpaux_transfer()
251 	u32 value;  in tegra_dpaux_irq()  local
254 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
255 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
257 	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))  in tegra_dpaux_irq()
260 	if (value & DPAUX_INTR_IRQ_EVENT) {  in tegra_dpaux_irq()
264 	if (value & DPAUX_INTR_AUX_DONE)  in tegra_dpaux_irq()
274 	u32 value;  in tegra_dpaux_probe()  local
373 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_probe()
374 	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_probe()
375 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_probe()
377 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_probe()
378 	value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |  in tegra_dpaux_probe()
381 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_probe()
384 	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |  in tegra_dpaux_probe()
386 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);  in tegra_dpaux_probe()
387 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_probe()
401 	u32 value;  in tegra_dpaux_remove()  local
404 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_remove()
405 	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_remove()
406 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_remove()
515 	u32 value;  in tegra_dpaux_detect()  local
517 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_detect()
519 	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)  in tegra_dpaux_detect()
527 	u32 value;  in tegra_dpaux_enable()  local
529 	value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |  in tegra_dpaux_enable()
534 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_enable()
536 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
537 	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_enable()
538 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
545 	u32 value;  in tegra_dpaux_disable()  local
547 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()
548 	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_disable()
549 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()