59 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,  in tegra_dpaux_readl()  argument
62 	return readl(dpaux->regs + (offset << 2));  in tegra_dpaux_readl()
65 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,  in tegra_dpaux_writel()  argument
68 	writel(value, dpaux->regs + (offset << 2));  in tegra_dpaux_writel()
71 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,  in tegra_dpaux_write_fifo()  argument
83 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));  in tegra_dpaux_write_fifo()
87 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,  in tegra_dpaux_read_fifo()  argument
96 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));  in tegra_dpaux_read_fifo()
107 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in tegra_dpaux_transfer()  local
173 	tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);  in tegra_dpaux_transfer()
174 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
177 		tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);  in tegra_dpaux_transfer()
182 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
184 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
186 	status = wait_for_completion_timeout(&dpaux->complete, timeout);  in tegra_dpaux_transfer()
191 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
192 	tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
231 			tegra_dpaux_read_fifo(dpaux, msg->buffer, count);  in tegra_dpaux_transfer()
241 	struct tegra_dpaux *dpaux = work_to_dpaux(work);  in tegra_dpaux_hotplug()  local
243 	if (dpaux->output)  in tegra_dpaux_hotplug()
244 		drm_helper_hpd_irq_event(dpaux->output->connector.dev);  in tegra_dpaux_hotplug()
249 	struct tegra_dpaux *dpaux = data;  in tegra_dpaux_irq()  local
254 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
255 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
258 		schedule_work(&dpaux->work);  in tegra_dpaux_irq()
265 		complete(&dpaux->complete);  in tegra_dpaux_irq()
272 	struct tegra_dpaux *dpaux;  in tegra_dpaux_probe()  local
277 	dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);  in tegra_dpaux_probe()
278 	if (!dpaux)  in tegra_dpaux_probe()
281 	INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);  in tegra_dpaux_probe()
282 	init_completion(&dpaux->complete);  in tegra_dpaux_probe()
283 	INIT_LIST_HEAD(&dpaux->list);  in tegra_dpaux_probe()
284 	dpaux->dev = &pdev->dev;  in tegra_dpaux_probe()
287 	dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);  in tegra_dpaux_probe()
288 	if (IS_ERR(dpaux->regs))  in tegra_dpaux_probe()
289 		return PTR_ERR(dpaux->regs);  in tegra_dpaux_probe()
291 	dpaux->irq = platform_get_irq(pdev, 0);  in tegra_dpaux_probe()
292 	if (dpaux->irq < 0) {  in tegra_dpaux_probe()
297 	dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");  in tegra_dpaux_probe()
298 	if (IS_ERR(dpaux->rst)) {  in tegra_dpaux_probe()
300 			PTR_ERR(dpaux->rst));  in tegra_dpaux_probe()
301 		return PTR_ERR(dpaux->rst);  in tegra_dpaux_probe()
304 	dpaux->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_dpaux_probe()
305 	if (IS_ERR(dpaux->clk)) {  in tegra_dpaux_probe()
307 			PTR_ERR(dpaux->clk));  in tegra_dpaux_probe()
308 		return PTR_ERR(dpaux->clk);  in tegra_dpaux_probe()
311 	err = clk_prepare_enable(dpaux->clk);  in tegra_dpaux_probe()
318 	reset_control_deassert(dpaux->rst);  in tegra_dpaux_probe()
320 	dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");  in tegra_dpaux_probe()
321 	if (IS_ERR(dpaux->clk_parent)) {  in tegra_dpaux_probe()
323 			PTR_ERR(dpaux->clk_parent));  in tegra_dpaux_probe()
324 		return PTR_ERR(dpaux->clk_parent);  in tegra_dpaux_probe()
327 	err = clk_prepare_enable(dpaux->clk_parent);  in tegra_dpaux_probe()
334 	err = clk_set_rate(dpaux->clk_parent, 270000000);  in tegra_dpaux_probe()
341 	dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");  in tegra_dpaux_probe()
342 	if (IS_ERR(dpaux->vdd)) {  in tegra_dpaux_probe()
344 			PTR_ERR(dpaux->vdd));  in tegra_dpaux_probe()
345 		return PTR_ERR(dpaux->vdd);  in tegra_dpaux_probe()
348 	err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,  in tegra_dpaux_probe()
349 			       dev_name(dpaux->dev), dpaux);  in tegra_dpaux_probe()
351 		dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",  in tegra_dpaux_probe()
352 			dpaux->irq, err);  in tegra_dpaux_probe()
356 	disable_irq(dpaux->irq);  in tegra_dpaux_probe()
358 	dpaux->aux.transfer = tegra_dpaux_transfer;  in tegra_dpaux_probe()
359 	dpaux->aux.dev = &pdev->dev;  in tegra_dpaux_probe()
361 	err = drm_dp_aux_register(&dpaux->aux);  in tegra_dpaux_probe()
373 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_probe()
375 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_probe()
377 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_probe()
381 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_probe()
386 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);  in tegra_dpaux_probe()
387 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_probe()
390 	list_add_tail(&dpaux->list, &dpaux_list);  in tegra_dpaux_probe()
393 	platform_set_drvdata(pdev, dpaux);  in tegra_dpaux_probe()
400 	struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);  in tegra_dpaux_remove()  local
404 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_remove()
406 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_remove()
408 	drm_dp_aux_unregister(&dpaux->aux);  in tegra_dpaux_remove()
411 	list_del(&dpaux->list);  in tegra_dpaux_remove()
414 	cancel_work_sync(&dpaux->work);  in tegra_dpaux_remove()
416 	clk_disable_unprepare(dpaux->clk_parent);  in tegra_dpaux_remove()
417 	reset_control_assert(dpaux->rst);  in tegra_dpaux_remove()
418 	clk_disable_unprepare(dpaux->clk);  in tegra_dpaux_remove()
441 	struct tegra_dpaux *dpaux;  in tegra_dpaux_find_by_of_node()  local
445 	list_for_each_entry(dpaux, &dpaux_list, list)  in tegra_dpaux_find_by_of_node()
446 		if (np == dpaux->dev->of_node) {  in tegra_dpaux_find_by_of_node()
448 			return dpaux;  in tegra_dpaux_find_by_of_node()
456 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)  in tegra_dpaux_attach()  argument
462 	dpaux->output = output;  in tegra_dpaux_attach()
464 	err = regulator_enable(dpaux->vdd);  in tegra_dpaux_attach()
473 		status = tegra_dpaux_detect(dpaux);  in tegra_dpaux_attach()
475 			enable_irq(dpaux->irq);  in tegra_dpaux_attach()
485 int tegra_dpaux_detach(struct tegra_dpaux *dpaux)  in tegra_dpaux_detach()  argument
490 	disable_irq(dpaux->irq);  in tegra_dpaux_detach()
492 	err = regulator_disable(dpaux->vdd);  in tegra_dpaux_detach()
501 		status = tegra_dpaux_detect(dpaux);  in tegra_dpaux_detach()
503 			dpaux->output = NULL;  in tegra_dpaux_detach()
513 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)  in tegra_dpaux_detect()  argument
517 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_detect()
525 int tegra_dpaux_enable(struct tegra_dpaux *dpaux)  in tegra_dpaux_enable()  argument
534 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_enable()
536 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
538 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
543 int tegra_dpaux_disable(struct tegra_dpaux *dpaux)  in tegra_dpaux_disable()  argument
547 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()
549 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()
554 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)  in tegra_dpaux_prepare()  argument
558 	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,  in tegra_dpaux_prepare()
566 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,  in tegra_dpaux_train()  argument
574 	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);  in tegra_dpaux_train()
587 	err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,  in tegra_dpaux_train()
594 	err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);  in tegra_dpaux_train()
612 		dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);  in tegra_dpaux_train()
616 	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);  in tegra_dpaux_train()