152 	u32 tmp;  in vtg_set_mode()  local
167 	tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;  in vtg_set_mode()
168 	tmp |= HDMI_DELAY;  in vtg_set_mode()
169 	writel(tmp, vtg->regs + VTG_H_HD_1);  in vtg_set_mode()
171 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
172 	tmp |= 1;  in vtg_set_mode()
173 	writel(tmp, vtg->regs + VTG_TOP_V_VD_1);  in vtg_set_mode()
174 	writel(tmp, vtg->regs + VTG_BOT_V_VD_1);  in vtg_set_mode()
176 	tmp = HDMI_DELAY << 16;  in vtg_set_mode()
177 	tmp |= HDMI_DELAY;  in vtg_set_mode()
178 	writel(tmp, vtg->regs + VTG_TOP_V_HD_1);  in vtg_set_mode()
179 	writel(tmp, vtg->regs + VTG_BOT_V_HD_1);  in vtg_set_mode()
182 	tmp = (mode->hsync_end - mode->hsync_start) << 16;  in vtg_set_mode()
183 	writel(tmp, vtg->regs + VTG_H_HD_2);  in vtg_set_mode()
185 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
186 	tmp |= 1;  in vtg_set_mode()
187 	writel(tmp, vtg->regs + VTG_TOP_V_VD_2);  in vtg_set_mode()
188 	writel(tmp, vtg->regs + VTG_BOT_V_VD_2);  in vtg_set_mode()
193 	tmp = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16;  in vtg_set_mode()
194 	tmp |= mode->htotal + AWG_DELAY_HD;  in vtg_set_mode()
195 	writel(tmp, vtg->regs + VTG_H_HD_3);  in vtg_set_mode()
197 	tmp = (mode->vsync_end - mode->vsync_start) << 16;  in vtg_set_mode()
198 	tmp |= mode->vtotal;  in vtg_set_mode()
199 	writel(tmp, vtg->regs + VTG_TOP_V_VD_3);  in vtg_set_mode()
200 	writel(tmp, vtg->regs + VTG_BOT_V_VD_3);  in vtg_set_mode()
202 	tmp = (mode->htotal + AWG_DELAY_HD) << 16;  in vtg_set_mode()
203 	tmp |= mode->htotal + AWG_DELAY_HD;  in vtg_set_mode()
204 	writel(tmp, vtg->regs + VTG_TOP_V_HD_3);  in vtg_set_mode()
205 	writel(tmp, vtg->regs + VTG_BOT_V_HD_3);  in vtg_set_mode()
208 	tmp = (mode->hsync_end - mode->hsync_start) << 16;  in vtg_set_mode()
209 	writel(tmp, vtg->regs + VTG_H_HD_4);  in vtg_set_mode()
211 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
212 	tmp |= 1;  in vtg_set_mode()
213 	writel(tmp, vtg->regs + VTG_TOP_V_VD_4);  in vtg_set_mode()
214 	writel(tmp, vtg->regs + VTG_BOT_V_VD_4);  in vtg_set_mode()