29 void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,  in savage_emit_clip_rect_s3d()  argument
32 	uint32_t scstart = dev_priv->state.s3d.new_scstart;  in savage_emit_clip_rect_s3d()
33 	uint32_t scend = dev_priv->state.s3d.new_scend;  in savage_emit_clip_rect_s3d()
40 	if (scstart != dev_priv->state.s3d.scstart ||  in savage_emit_clip_rect_s3d()
41 	    scend != dev_priv->state.s3d.scend) {  in savage_emit_clip_rect_s3d()
48 		dev_priv->state.s3d.scstart = scstart;  in savage_emit_clip_rect_s3d()
49 		dev_priv->state.s3d.scend = scend;  in savage_emit_clip_rect_s3d()
50 		dev_priv->waiting = 1;  in savage_emit_clip_rect_s3d()
55 void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,  in savage_emit_clip_rect_s4()  argument
58 	uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;  in savage_emit_clip_rect_s4()
59 	uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;  in savage_emit_clip_rect_s4()
66 	if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||  in savage_emit_clip_rect_s4()
67 	    drawctrl1 != dev_priv->state.s4.drawctrl1) {  in savage_emit_clip_rect_s4()
74 		dev_priv->state.s4.drawctrl0 = drawctrl0;  in savage_emit_clip_rect_s4()
75 		dev_priv->state.s4.drawctrl1 = drawctrl1;  in savage_emit_clip_rect_s4()
76 		dev_priv->waiting = 1;  in savage_emit_clip_rect_s4()
81 static int savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit,  in savage_verify_texaddr()  argument
90 		if (addr < dev_priv->texture_offset ||  in savage_verify_texaddr()
91 		    addr >= dev_priv->texture_offset + dev_priv->texture_size) {  in savage_verify_texaddr()
98 		if (!dev_priv->agp_textures) {  in savage_verify_texaddr()
104 		if (addr < dev_priv->agp_textures->offset ||  in savage_verify_texaddr()
105 		    addr >= (dev_priv->agp_textures->offset +  in savage_verify_texaddr()
106 			     dev_priv->agp_textures->size)) {  in savage_verify_texaddr()
118 		dev_priv->state.where = regs[reg - start]
123 		dev_priv->state.where = (tmp & (mask)) |	\
124 			(dev_priv->state.where & ~(mask));	\
128 static int savage_verify_state_s3d(drm_savage_private_t * dev_priv,  in savage_verify_state_s3d()  argument
150 		if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)  in savage_verify_state_s3d()
151 			return savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s3d()
152 						dev_priv->state.s3d.texaddr);  in savage_verify_state_s3d()
158 static int savage_verify_state_s4(drm_savage_private_t * dev_priv,  in savage_verify_state_s4()  argument
183 		if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)  in savage_verify_state_s4()
184 			ret |= savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s4()
185 						dev_priv->state.s4.texaddr0);  in savage_verify_state_s4()
186 		if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)  in savage_verify_state_s4()
187 			ret |= savage_verify_texaddr(dev_priv, 1,  in savage_verify_state_s4()
188 						dev_priv->state.s4.texaddr1);  in savage_verify_state_s4()
197 static int savage_dispatch_state(drm_savage_private_t * dev_priv,  in savage_dispatch_state()  argument
211 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_state()
212 		ret = savage_verify_state_s3d(dev_priv, start, count, regs);  in savage_dispatch_state()
229 		ret = savage_verify_state_s4(dev_priv, start, count, regs);  in savage_dispatch_state()
253 		dev_priv->waiting = 1;  in savage_dispatch_state()
278 static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv,  in savage_dispatch_dma_prim()  argument
323 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_prim()
353 	if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {  in savage_dispatch_dma_prim()
356 		BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);  in savage_dispatch_dma_prim()
357 		dev_priv->state.common.vbaddr = dmabuf->bus_address;  in savage_dispatch_dma_prim()
359 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {  in savage_dispatch_dma_prim()
368 		dev_priv->waiting = 0;  in savage_dispatch_dma_prim()
391 		} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_prim()
418 static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv,  in savage_dispatch_vb_prim()  argument
460 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_vb_prim()
536 static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv,  in savage_dispatch_dma_idx()  argument
579 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_idx()
603 	if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {  in savage_dispatch_dma_idx()
606 		BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);  in savage_dispatch_dma_idx()
607 		dev_priv->state.common.vbaddr = dmabuf->bus_address;  in savage_dispatch_dma_idx()
609 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {  in savage_dispatch_dma_idx()
618 		dev_priv->waiting = 0;  in savage_dispatch_dma_idx()
650 		} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_dma_idx()
677 static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv,  in savage_dispatch_vb_idx()  argument
717 	if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {  in savage_dispatch_vb_idx()
791 static int savage_dispatch_clear(drm_savage_private_t * dev_priv,  in savage_dispatch_clear()  argument
834 				DMA_WRITE(dev_priv->front_offset);  in savage_dispatch_clear()
835 				DMA_WRITE(dev_priv->front_bd);  in savage_dispatch_clear()
838 				DMA_WRITE(dev_priv->back_offset);  in savage_dispatch_clear()
839 				DMA_WRITE(dev_priv->back_bd);  in savage_dispatch_clear()
842 				DMA_WRITE(dev_priv->depth_offset);  in savage_dispatch_clear()
843 				DMA_WRITE(dev_priv->depth_bd);  in savage_dispatch_clear()
863 static int savage_dispatch_swap(drm_savage_private_t * dev_priv,  in savage_dispatch_swap()  argument
880 		DMA_WRITE(dev_priv->back_offset);  in savage_dispatch_swap()
881 		DMA_WRITE(dev_priv->back_bd);  in savage_dispatch_swap()
892 static int savage_dispatch_draw(drm_savage_private_t * dev_priv,  in savage_dispatch_draw()  argument
906 		dev_priv->emit_clip_rect(dev_priv, &boxes[i]);  in savage_dispatch_draw()
916 					dev_priv, &cmd_header, dmabuf);  in savage_dispatch_draw()
920 					dev_priv, &cmd_header,  in savage_dispatch_draw()
926 				ret = savage_dispatch_dma_idx(dev_priv,  in savage_dispatch_draw()
934 				ret = savage_dispatch_vb_idx(dev_priv,  in savage_dispatch_draw()
958 	drm_savage_private_t *dev_priv = dev->dev_private;  in savage_bci_cmdbuf()  local
1039 	dev_priv->waiting = 1;  in savage_bci_cmdbuf()
1074 				      dev_priv, first_draw_cmd,  in savage_bci_cmdbuf()
1097 			ret = savage_dispatch_state(dev_priv, &cmd_header,  in savage_bci_cmdbuf()
1110 			ret = savage_dispatch_clear(dev_priv, &cmd_header,  in savage_bci_cmdbuf()
1118 			ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox,  in savage_bci_cmdbuf()
1137 			dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf,  in savage_bci_cmdbuf()
1151 		event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);  in savage_bci_cmdbuf()
1152 		SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);  in savage_bci_cmdbuf()