Lines Matching refs:VOP_REG
38 #define VOP_REG(off, _mask, s) \ macro
258 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
259 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
260 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
261 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
262 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
263 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
264 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
265 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
266 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
267 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
268 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
269 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
270 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
271 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
272 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
273 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
274 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
275 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
276 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
277 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
278 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
279 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
280 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
281 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
282 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
289 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
290 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
291 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
292 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
293 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
294 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
295 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
296 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
297 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
298 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
299 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
300 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
306 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
307 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
308 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
309 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
310 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
311 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
312 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
313 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
314 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
318 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
319 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
320 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
321 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
322 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
323 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
324 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
325 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
326 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
327 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
328 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
329 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
330 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
331 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
332 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
333 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
334 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
335 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),