60 			   struct radeon_ring *ring)  in vce_v1_0_get_rptr()  argument
62 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_get_rptr()
77 			   struct radeon_ring *ring)  in vce_v1_0_get_wptr()  argument
79 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_get_wptr()
94 		       struct radeon_ring *ring)  in vce_v1_0_set_wptr()  argument
96 	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)  in vce_v1_0_set_wptr()
97 		WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_set_wptr()
99 		WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_set_wptr()
291 	struct radeon_ring *ring;  in vce_v1_0_start()  local
297 	ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];  in vce_v1_0_start()
298 	WREG32(VCE_RB_RPTR, ring->wptr);  in vce_v1_0_start()
299 	WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_start()
300 	WREG32(VCE_RB_BASE_LO, ring->gpu_addr);  in vce_v1_0_start()
301 	WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
302 	WREG32(VCE_RB_SIZE, ring->ring_size / 4);  in vce_v1_0_start()
304 	ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];  in vce_v1_0_start()
305 	WREG32(VCE_RB_RPTR2, ring->wptr);  in vce_v1_0_start()
306 	WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_start()
307 	WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v1_0_start()
308 	WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
309 	WREG32(VCE_RB_SIZE2, ring->ring_size / 4);  in vce_v1_0_start()
358 	struct radeon_ring *ring;  in vce_v1_0_init()  local
365 	ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];  in vce_v1_0_init()
366 	ring->ready = true;  in vce_v1_0_init()
367 	r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);  in vce_v1_0_init()
369 		ring->ready = false;  in vce_v1_0_init()
373 	ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];  in vce_v1_0_init()
374 	ring->ready = true;  in vce_v1_0_init()
375 	r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);  in vce_v1_0_init()
377 		ring->ready = false;  in vce_v1_0_init()