97 		WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_set_wptr()
99 		WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_set_wptr()
109 		WREG32(VCE_CLOCK_GATING_A, tmp);  in vce_v1_0_enable_mgcg()
114 		WREG32(VCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
118 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
122 		WREG32(VCE_CLOCK_GATING_A, tmp);  in vce_v1_0_enable_mgcg()
127 		WREG32(VCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
131 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
141 	WREG32(VCE_CLOCK_GATING_A, tmp);  in vce_v1_0_init_cg()
146 	WREG32(VCE_CLOCK_GATING_B, tmp);  in vce_v1_0_init_cg()
150 	WREG32(VCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_init_cg()
154 	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_init_cg()
225 	WREG32(VCE_CLOCK_GATING_B, 0);  in vce_v1_0_resume()
229 	WREG32(VCE_LMI_CTRL, 0x00398000);  in vce_v1_0_resume()
231 	WREG32(VCE_LMI_SWAP_CNTL, 0);  in vce_v1_0_resume()
232 	WREG32(VCE_LMI_SWAP_CNTL1, 0);  in vce_v1_0_resume()
233 	WREG32(VCE_LMI_VM_CTRL, 0);  in vce_v1_0_resume()
235 	WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);  in vce_v1_0_resume()
239 	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);  in vce_v1_0_resume()
240 	WREG32(VCE_VCPU_CACHE_SIZE0, size);  in vce_v1_0_resume()
244 	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);  in vce_v1_0_resume()
245 	WREG32(VCE_VCPU_CACHE_SIZE1, size);  in vce_v1_0_resume()
249 	WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);  in vce_v1_0_resume()
250 	WREG32(VCE_VCPU_CACHE_SIZE2, size);  in vce_v1_0_resume()
254 	WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);  in vce_v1_0_resume()
298 	WREG32(VCE_RB_RPTR, ring->wptr);  in vce_v1_0_start()
299 	WREG32(VCE_RB_WPTR, ring->wptr);  in vce_v1_0_start()
300 	WREG32(VCE_RB_BASE_LO, ring->gpu_addr);  in vce_v1_0_start()
301 	WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
302 	WREG32(VCE_RB_SIZE, ring->ring_size / 4);  in vce_v1_0_start()
305 	WREG32(VCE_RB_RPTR2, ring->wptr);  in vce_v1_0_start()
306 	WREG32(VCE_RB_WPTR2, ring->wptr);  in vce_v1_0_start()
307 	WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v1_0_start()
308 	WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
309 	WREG32(VCE_RB_SIZE2, ring->ring_size / 4);  in vce_v1_0_start()