42 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in uvd_v2_2_fence_emit()  local
43 	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;  in uvd_v2_2_fence_emit()
45 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v2_2_fence_emit()
46 	radeon_ring_write(ring, fence->seq);  in uvd_v2_2_fence_emit()
47 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
48 	radeon_ring_write(ring, lower_32_bits(addr));  in uvd_v2_2_fence_emit()
49 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
50 	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);  in uvd_v2_2_fence_emit()
51 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
52 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
54 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
55 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
56 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
57 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
58 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
59 	radeon_ring_write(ring, 2);  in uvd_v2_2_fence_emit()
73 			     struct radeon_ring *ring,  in uvd_v2_2_semaphore_emit()  argument
79 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));  in uvd_v2_2_semaphore_emit()
80 	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
82 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));  in uvd_v2_2_semaphore_emit()
83 	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
85 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));  in uvd_v2_2_semaphore_emit()
86 	radeon_ring_write(ring, emit_wait ? 1 : 0);  in uvd_v2_2_semaphore_emit()