40 			   struct radeon_ring *ring)  in uvd_v1_0_get_rptr()  argument
54 			   struct radeon_ring *ring)  in uvd_v1_0_get_wptr()  argument
68 		       struct radeon_ring *ring)  in uvd_v1_0_set_wptr()  argument
70 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_set_wptr()
84 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in uvd_v1_0_fence_emit()  local
85 	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;  in uvd_v1_0_fence_emit()
87 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
88 	radeon_ring_write(ring, addr & 0xffffffff);  in uvd_v1_0_fence_emit()
89 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
90 	radeon_ring_write(ring, fence->seq);  in uvd_v1_0_fence_emit()
91 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
92 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
94 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
95 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
96 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
97 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
98 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
99 	radeon_ring_write(ring, 2);  in uvd_v1_0_fence_emit()
158 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_init()  local
172 	ring->ready = true;  in uvd_v1_0_init()
173 	r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);  in uvd_v1_0_init()
175 		ring->ready = false;  in uvd_v1_0_init()
179 	r = radeon_ring_lock(rdev, ring, 10);  in uvd_v1_0_init()
186 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
187 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
190 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
191 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
194 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
195 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
198 	radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v1_0_init()
199 	radeon_ring_write(ring, 0x8);  in uvd_v1_0_init()
201 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));  in uvd_v1_0_init()
202 	radeon_ring_write(ring, 3);  in uvd_v1_0_init()
204 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_init()
249 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_fini()  local
252 	ring->ready = false;  in uvd_v1_0_fini()
264 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_start()  local
363 	WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v1_0_start()
369 	ring->wptr = RREG32(UVD_RBC_RB_RPTR);  in uvd_v1_0_start()
370 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_start()
373 	WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v1_0_start()
376 	rb_bufsz = order_base_2(ring->ring_size);  in uvd_v1_0_start()
420 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ring_test()  argument
427 	r = radeon_ring_lock(rdev, ring, 3);  in uvd_v1_0_ring_test()
430 			  ring->idx, r);  in uvd_v1_0_ring_test()
433 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v1_0_ring_test()
434 	radeon_ring_write(ring, 0xDEADBEEF);  in uvd_v1_0_ring_test()
435 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_ring_test()
445 			 ring->idx, i);  in uvd_v1_0_ring_test()
448 			  ring->idx, tmp);  in uvd_v1_0_ring_test()
465 			     struct radeon_ring *ring,  in uvd_v1_0_semaphore_emit()  argument
483 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in uvd_v1_0_ib_execute()  local
485 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));  in uvd_v1_0_ib_execute()
486 	radeon_ring_write(ring, ib->gpu_addr);  in uvd_v1_0_ib_execute()
487 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));  in uvd_v1_0_ib_execute()
488 	radeon_ring_write(ring, ib->length_dw);  in uvd_v1_0_ib_execute()
499 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ib_test()  argument
513 	r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);  in uvd_v1_0_ib_test()
519 	r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);  in uvd_v1_0_ib_test()
530 	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);  in uvd_v1_0_ib_test()