70 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_set_wptr()
123 	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);  in uvd_v1_0_resume()
124 	WREG32(UVD_VCPU_CACHE_SIZE0, size);  in uvd_v1_0_resume()
128 	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);  in uvd_v1_0_resume()
129 	WREG32(UVD_VCPU_CACHE_SIZE1, size);  in uvd_v1_0_resume()
133 	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);  in uvd_v1_0_resume()
134 	WREG32(UVD_VCPU_CACHE_SIZE2, size);  in uvd_v1_0_resume()
138 	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v1_0_resume()
142 	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v1_0_resume()
144 	WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));  in uvd_v1_0_resume()
216 			WREG32(MC_CONFIG, 0);  in uvd_v1_0_init()
217 			WREG32(MC_CONFIG, 1 << 4);  in uvd_v1_0_init()
218 			WREG32(RS_DQ_RD_RET_CONF, 0x3f);  in uvd_v1_0_init()
219 			WREG32(MC_CONFIG, 0x1f);  in uvd_v1_0_init()
273 	WREG32(UVD_CGC_GATE, 0);  in uvd_v1_0_start()
284 	WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |  in uvd_v1_0_start()
294 	WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |  in uvd_v1_0_start()
302 	WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v1_0_start()
303 	WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v1_0_start()
305 	WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v1_0_start()
306 	WREG32(UVD_MPC_SET_MUXA1, 0x0);  in uvd_v1_0_start()
307 	WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v1_0_start()
308 	WREG32(UVD_MPC_SET_MUXB1, 0x0);  in uvd_v1_0_start()
309 	WREG32(UVD_MPC_SET_ALU, 0);  in uvd_v1_0_start()
310 	WREG32(UVD_MPC_SET_MUX, 0x88);  in uvd_v1_0_start()
313 	WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);  in uvd_v1_0_start()
317 	WREG32(UVD_VCPU_CNTL,  1 << 9);  in uvd_v1_0_start()
325 	WREG32(UVD_SOFT_RESET, 0);  in uvd_v1_0_start()
357 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);  in uvd_v1_0_start()
360 	WREG32(UVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v1_0_start()
363 	WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v1_0_start()
367 	WREG32(UVD_RBC_RB_RPTR, 0x0);  in uvd_v1_0_start()
370 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_start()
373 	WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v1_0_start()
393 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);  in uvd_v1_0_stop()
401 	WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);  in uvd_v1_0_stop()
405 	WREG32(UVD_VCPU_CNTL, 0x0);  in uvd_v1_0_stop()
426 	WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v1_0_ring_test()