588 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_divider_value()  local
595 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_divider_value()
598 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_divider_value()
605 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);  in trinity_set_divider_value()
608 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);  in trinity_set_divider_value()
615 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_ds_dividers()  local
617 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ds_dividers()
620 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_ds_dividers()
627 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_ss_dividers()  local
629 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ss_dividers()
632 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_ss_dividers()
640 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_vid()  local
642 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
645 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_vid()
647 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
650 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_vid()
657 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_allos_gnb_slow()  local
659 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_allos_gnb_slow()
662 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);  in trinity_set_allos_gnb_slow()
669 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_force_nbp_state()  local
671 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_force_nbp_state()
674 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);  in trinity_set_force_nbp_state()
681 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_display_wm()  local
683 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_display_wm()
686 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_display_wm()
693 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_vce_wm()  local
695 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_vce_wm()
698 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_vce_wm()
705 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_set_at()  local
707 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);  in trinity_set_at()
710 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);  in trinity_set_at()
736 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;  in trinity_power_level_enable_disable()  local
738 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_power_level_enable_disable()
742 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_power_level_enable_disable()