Lines Matching refs:vddc
1773 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1778 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1811 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1814 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2349 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2358 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2548 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2549 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2550 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2551 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2996 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules() local
3044 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3045 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3053 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3054 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3103 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3106 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3119 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3130 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3136 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3137 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3165 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3166 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3169 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3175 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3178 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3183 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3184 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3190 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3248 u16 vddc, count = 0; in si_get_leakage_vddc() local
3252 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3254 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3255 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4179 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4182 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4194 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4197 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4204 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4433 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4434 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4440 &table->initialState.levels[0].vddc, in si_populate_smc_initial_state()
4444 table->initialState.levels[0].vddc.index, in si_populate_smc_initial_state()
4457 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4460 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4527 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4532 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4535 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4546 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4550 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4555 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4559 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4573 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4664 state->levels[0].std_vddc = state->levels[0].vddc; in si_populate_ulv_state()
4771 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5059 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5064 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5069 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5083 pl->vddc, in si_convert_power_level_to_smc()
5086 &level->vddc); in si_convert_power_level_to_smc()
5175 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5312 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5685 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6761 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6770 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6773 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6776 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6792 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6793 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6795 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6796 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6800 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
6801 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6804 pl->vddc = vddc; in si_parse_pplib_clock_info()
6813 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7105 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()