1869 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_powertune_defaults()  local
1873 		si_pi->cac_weights = cac_weights_tahiti;  in si_initialize_powertune_defaults()
1874 		si_pi->lcac_config = lcac_tahiti;  in si_initialize_powertune_defaults()
1875 		si_pi->cac_override = cac_override_tahiti;  in si_initialize_powertune_defaults()
1876 		si_pi->powertune_data = &powertune_data_tahiti;  in si_initialize_powertune_defaults()
1877 		si_pi->dte_data = dte_data_tahiti;  in si_initialize_powertune_defaults()
1881 			si_pi->dte_data.enable_dte_by_default = true;  in si_initialize_powertune_defaults()
1884 			si_pi->dte_data = dte_data_new_zealand;  in si_initialize_powertune_defaults()
1890 			si_pi->dte_data = dte_data_aruba_pro;  in si_initialize_powertune_defaults()
1894 			si_pi->dte_data = dte_data_malta;  in si_initialize_powertune_defaults()
1898 			si_pi->dte_data = dte_data_tahiti_pro;  in si_initialize_powertune_defaults()
1902 			if (si_pi->dte_data.enable_dte_by_default == true)  in si_initialize_powertune_defaults()
1910 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1911 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1912 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1913 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1914 			si_pi->dte_data = dte_data_curacao_xt;  in si_initialize_powertune_defaults()
1919 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1920 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1921 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1922 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1923 			si_pi->dte_data = dte_data_curacao_pro;  in si_initialize_powertune_defaults()
1928 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1929 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1930 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1931 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1932 			si_pi->dte_data = dte_data_neptune_xt;  in si_initialize_powertune_defaults()
1936 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1937 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1938 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1939 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1940 			si_pi->dte_data = dte_data_pitcairn;  in si_initialize_powertune_defaults()
1944 		si_pi->lcac_config = lcac_cape_verde;  in si_initialize_powertune_defaults()
1945 		si_pi->cac_override = cac_override_cape_verde;  in si_initialize_powertune_defaults()
1946 		si_pi->powertune_data = &powertune_data_cape_verde;  in si_initialize_powertune_defaults()
1953 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1954 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1957 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1958 			si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
1962 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1963 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1967 			si_pi->cac_weights = cac_weights_chelsea_xt;  in si_initialize_powertune_defaults()
1968 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1971 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1972 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1975 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1976 			si_pi->dte_data = dte_data_venus_xtx;  in si_initialize_powertune_defaults()
1979 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1980 			si_pi->dte_data = dte_data_venus_xt;  in si_initialize_powertune_defaults()
1986 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1987 			si_pi->dte_data = dte_data_venus_pro;  in si_initialize_powertune_defaults()
1990 			si_pi->cac_weights = cac_weights_cape_verde;  in si_initialize_powertune_defaults()
1991 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2000 			si_pi->cac_weights = cac_weights_mars_pro;  in si_initialize_powertune_defaults()
2001 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2002 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2003 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2004 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2011 			si_pi->cac_weights = cac_weights_mars_xt;  in si_initialize_powertune_defaults()
2012 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2013 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2014 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2015 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2021 			si_pi->cac_weights = cac_weights_oland_pro;  in si_initialize_powertune_defaults()
2022 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2023 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2024 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2025 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2029 			si_pi->cac_weights = cac_weights_oland_xt;  in si_initialize_powertune_defaults()
2030 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2031 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2032 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2033 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2037 			si_pi->cac_weights = cac_weights_oland;  in si_initialize_powertune_defaults()
2038 			si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2039 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2040 			si_pi->powertune_data = &powertune_data_oland;  in si_initialize_powertune_defaults()
2041 			si_pi->dte_data = dte_data_oland;  in si_initialize_powertune_defaults()
2045 		si_pi->cac_weights = cac_weights_hainan;  in si_initialize_powertune_defaults()
2046 		si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2047 		si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2048 		si_pi->powertune_data = &powertune_data_hainan;  in si_initialize_powertune_defaults()
2049 		si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
2059 	si_pi->enable_dte = false;  in si_initialize_powertune_defaults()
2061 	if (si_pi->powertune_data->enable_powertune_by_default) {  in si_initialize_powertune_defaults()
2064 		if (si_pi->dte_data.enable_dte_by_default) {  in si_initialize_powertune_defaults()
2065 			si_pi->enable_dte = true;  in si_initialize_powertune_defaults()
2067 				si_update_dte_from_pl2(rdev, &si_pi->dte_data);  in si_initialize_powertune_defaults()
2078 		si_pi->dyn_powertune_data.l2_lta_window_size =  in si_initialize_powertune_defaults()
2079 			si_pi->powertune_data->l2_lta_window_size_default;  in si_initialize_powertune_defaults()
2080 		si_pi->dyn_powertune_data.lts_truncate =  in si_initialize_powertune_defaults()
2081 			si_pi->powertune_data->lts_truncate_default;  in si_initialize_powertune_defaults()
2084 		si_pi->dyn_powertune_data.l2_lta_window_size = 0;  in si_initialize_powertune_defaults()
2085 		si_pi->dyn_powertune_data.lts_truncate = 0;  in si_initialize_powertune_defaults()
2088 	si_pi->dyn_powertune_data.disable_uvd_powertune = false;  in si_initialize_powertune_defaults()
2158 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits()  local
2161 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits()
2190 					   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +  in si_populate_smc_tdp_limits()
2194 					   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2198 		if (si_pi->enable_ppm) {  in si_populate_smc_tdp_limits()
2199 			papm_parm = &si_pi->papm_parm;  in si_populate_smc_tdp_limits()
2208 			ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,  in si_populate_smc_tdp_limits()
2211 						   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2223 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits_2()  local
2226 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits_2()
2238 					   (si_pi->state_table_start +  in si_populate_smc_tdp_limits_2()
2243 					   si_pi->sram_end);  in si_populate_smc_tdp_limits_2()
2276 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_should_disable_uvd_powertune()  local
2278 	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&  in si_should_disable_uvd_powertune()
2468 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_dte_tables()  local
2470 	struct si_dte_data *dte_data = &si_pi->dte_data;  in si_initialize_smc_dte_tables()
2477 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2479 	if (si_pi->enable_dte == false)  in si_initialize_smc_dte_tables()
2487 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2524 	ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,  in si_initialize_smc_dte_tables()
2525 				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);  in si_initialize_smc_dte_tables()
2534 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_cac_std_voltage_max_min()  local
2554 	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)  in si_get_cac_std_voltage_max_min()
2557 	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;  in si_get_cac_std_voltage_max_min()
2581 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_dte_leakage_table()  local
2598 							 &si_pi->powertune_data->leakage_coefficients,  in si_init_dte_leakage_table()
2601 							 si_pi->dyn_powertune_data.cac_leakage,  in si_init_dte_leakage_table()
2620 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_simplified_leakage_table()  local
2633 					   &si_pi->powertune_data->leakage_coefficients,  in si_init_simplified_leakage_table()
2634 					   si_pi->powertune_data->fixed_kt,  in si_init_simplified_leakage_table()
2636 					   si_pi->dyn_powertune_data.cac_leakage,  in si_init_simplified_leakage_table()
2654 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_cac_tables()  local
2670 	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);  in si_initialize_smc_cac_tables()
2673 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2674 	si_pi->dyn_powertune_data.dc_pwr_value =  in si_initialize_smc_cac_tables()
2675 		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];  in si_initialize_smc_cac_tables()
2676 	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);  in si_initialize_smc_cac_tables()
2677 	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;  in si_initialize_smc_cac_tables()
2679 	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;  in si_initialize_smc_cac_tables()
2690 	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)  in si_initialize_smc_cac_tables()
2702 	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);  in si_initialize_smc_cac_tables()
2703 	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;  in si_initialize_smc_cac_tables()
2704 	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;  in si_initialize_smc_cac_tables()
2708 	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);  in si_initialize_smc_cac_tables()
2712 	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;  in si_initialize_smc_cac_tables()
2716 	ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,  in si_initialize_smc_cac_tables()
2717 				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);  in si_initialize_smc_cac_tables()
2777 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_hardware_cac_manager()  local
2784 	ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);  in si_initialize_hardware_cac_manager()
2787 	ret = si_program_cac_config_registers(rdev, si_pi->cac_override);  in si_initialize_hardware_cac_manager()
2790 	ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);  in si_initialize_hardware_cac_manager()
2802 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_enable_smc_cac()  local
2823 				if (si_pi->enable_dte) {  in si_enable_smc_cac()
2830 			if (si_pi->enable_dte)  in si_enable_smc_cac()
2847 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_spll_table()  local
2857 	if (si_pi->spll_table_start == 0)  in si_init_smc_spll_table()
2903 		ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,  in si_init_smc_spll_table()
2905 					   si_pi->sram_end);  in si_init_smc_spll_table()
2942 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_lower_of_leakage_and_vce_voltage()  local
2945 	for (i = 0; i < si_pi->leakage_voltage.count; i++){  in si_get_lower_of_leakage_and_vce_voltage()
2946 		if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)  in si_get_lower_of_leakage_and_vce_voltage()
2947 			highest_leakage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_lower_of_leakage_and_vce_voltage()
2950 	if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))  in si_get_lower_of_leakage_and_vce_voltage()
3199 	struct si_power_info *si_pi = si_get_pi(rdev);
3202 				      si_pi->soft_regs_start + reg_offset, value,
3203 				      si_pi->sram_end);
3210 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_write_smc_soft_register()  local
3213 				       si_pi->soft_regs_start + reg_offset,  in si_write_smc_soft_register()
3214 				       value, si_pi->sram_end);  in si_write_smc_soft_register()
3247 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_vddc()  local
3255 			si_pi->leakage_voltage.entries[count].voltage = vddc;  in si_get_leakage_vddc()
3256 			si_pi->leakage_voltage.entries[count].leakage_index =  in si_get_leakage_vddc()
3261 	si_pi->leakage_voltage.count = count;  in si_get_leakage_vddc()
3267 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_voltage_from_leakage_index()  local
3282 	for (i = 0; i < si_pi->leakage_voltage.count; i++) {  in si_get_leakage_voltage_from_leakage_index()
3283 		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {  in si_get_leakage_voltage_from_leakage_index()
3284 			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_leakage_voltage_from_leakage_index()
3492 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_process_firmware_header()  local
3499 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3503         si_pi->state_table_start = tmp;  in si_process_firmware_header()
3508 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3512 	si_pi->soft_regs_start = tmp;  in si_process_firmware_header()
3517 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3521 	si_pi->mc_reg_table_start = tmp;  in si_process_firmware_header()
3526 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3530 	si_pi->fan_table_start = tmp;  in si_process_firmware_header()
3535 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3539 	si_pi->arb_table_start = tmp;  in si_process_firmware_header()
3544 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3548 	si_pi->cac_table_start = tmp;  in si_process_firmware_header()
3553 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3557 	si_pi->dte_table_start = tmp;  in si_process_firmware_header()
3562 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3566 	si_pi->spll_table_start = tmp;  in si_process_firmware_header()
3571 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3575 	si_pi->papm_cfg_table_start = tmp;  in si_process_firmware_header()
3582 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_read_clock_registers()  local
3584 	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in si_read_clock_registers()
3585 	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3586 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in si_read_clock_registers()
3587 	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in si_read_clock_registers()
3588 	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in si_read_clock_registers()
3589 	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in si_read_clock_registers()
3590 	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in si_read_clock_registers()
3591 	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in si_read_clock_registers()
3592 	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in si_read_clock_registers()
3593 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in si_read_clock_registers()
3594 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in si_read_clock_registers()
3595 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in si_read_clock_registers()
3596 	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3597 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in si_read_clock_registers()
3598 	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in si_read_clock_registers()
3894 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_firmware()  local
3900 	ret = si_load_smc_ucode(rdev, si_pi->sram_end);  in si_upload_firmware()
3974 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_construct_voltage_tables()  local
3987 	} else if (si_pi->voltage_control_svi2) {  in si_construct_voltage_tables()
4008 	if (si_pi->vddci_control_svi2) {  in si_construct_voltage_tables()
4018 						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4025 		if (si_pi->mvdd_voltage_table.count == 0) {  in si_construct_voltage_tables()
4030 		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)  in si_construct_voltage_tables()
4033 								 &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4036 	if (si_pi->vddc_phase_shed_control) {  in si_construct_voltage_tables()
4038 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);  in si_construct_voltage_tables()
4040 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4042 		if ((si_pi->vddc_phase_shed_table.count == 0) ||  in si_construct_voltage_tables()
4043 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))  in si_construct_voltage_tables()
4044 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4065 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_voltage_tables()  local
4068 	if (si_pi->voltage_control_svi2) {  in si_populate_smc_voltage_tables()
4070 			si_pi->svc_gpio_id);  in si_populate_smc_voltage_tables()
4072 			si_pi->svd_gpio_id);  in si_populate_smc_voltage_tables()
4097 		if (si_pi->mvdd_voltage_table.count) {  in si_populate_smc_voltage_tables()
4098 			si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);  in si_populate_smc_voltage_tables()
4101 				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);  in si_populate_smc_voltage_tables()
4104 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_voltage_tables()
4105 			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,  in si_populate_smc_voltage_tables()
4107 				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);  in si_populate_smc_voltage_tables()
4110 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);  in si_populate_smc_voltage_tables()
4113 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);  in si_populate_smc_voltage_tables()
4115 				si_pi->vddc_phase_shed_control = false;  in si_populate_smc_voltage_tables()
4147 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mvdd_value()  local
4153 			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;  in si_populate_mvdd_value()
4155 		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);  in si_populate_mvdd_value()
4242 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_arb_table_index()  local
4246 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);  in si_init_arb_table_index()
4253 	return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);  in si_init_arb_table_index()
4269 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_force_switch_to_arb_f0()  local
4273 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,  in si_force_switch_to_arb_f0()
4274 				     &tmp, si_pi->sram_end);  in si_force_switch_to_arb_f0()
4335 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_do_program_memory_timing_parameters()  local
4345 					   si_pi->arb_table_start +  in si_do_program_memory_timing_parameters()
4350 					   si_pi->sram_end);  in si_do_program_memory_timing_parameters()
4369 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_initial_mvdd_value()  local
4372 		return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,  in si_populate_initial_mvdd_value()
4373 						 si_pi->mvdd_bootup_value, voltage);  in si_populate_initial_mvdd_value()
4385 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_initial_state()  local
4390 		cpu_to_be32(si_pi->clock_registers.dll_cntl);  in si_populate_smc_initial_state()
4392 		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);  in si_populate_smc_initial_state()
4394 		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);  in si_populate_smc_initial_state()
4396 		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);  in si_populate_smc_initial_state()
4398 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);  in si_populate_smc_initial_state()
4400 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);  in si_populate_smc_initial_state()
4402 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);  in si_populate_smc_initial_state()
4404 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_initial_state()
4406 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_initial_state()
4412 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);  in si_populate_smc_initial_state()
4414 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);  in si_populate_smc_initial_state()
4416 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);  in si_populate_smc_initial_state()
4418 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);  in si_populate_smc_initial_state()
4420 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);  in si_populate_smc_initial_state()
4422 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);  in si_populate_smc_initial_state()
4454 	if (si_pi->vddc_phase_shed_control)  in si_populate_smc_initial_state()
4469 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;  in si_populate_smc_initial_state()
4506 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_acpi_state()  local
4507 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_populate_smc_acpi_state()
4508 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_populate_smc_acpi_state()
4509 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_populate_smc_acpi_state()
4510 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_populate_smc_acpi_state()
4511 	u32 dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_smc_acpi_state()
4512 	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_smc_acpi_state()
4513 	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_smc_acpi_state()
4514 	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_smc_acpi_state()
4515 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_smc_acpi_state()
4516 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_smc_acpi_state()
4517 	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_smc_acpi_state()
4538 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;  in si_populate_smc_acpi_state()
4540 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_acpi_state()
4563 										    si_pi->sys_pcie_mask,  in si_populate_smc_acpi_state()
4564 										    si_pi->boot_pcie_gen,  in si_populate_smc_acpi_state()
4567 		if (si_pi->vddc_phase_shed_control)  in si_populate_smc_acpi_state()
4606 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_acpi_state()
4608 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_acpi_state()
4646 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_ulv_state()  local
4647 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()
4675 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_program_ulv_memory_timing_parameters()  local
4676 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()
4689 				   si_pi->arb_table_start +  in si_program_ulv_memory_timing_parameters()
4694 				   si_pi->sram_end);  in si_program_ulv_memory_timing_parameters()
4709 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_table()  local
4711 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()
4712 	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;  in si_init_smc_table()
4789 	return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,  in si_init_smc_table()
4791 				    si_pi->sram_end);  in si_init_smc_table()
4799 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_calculate_sclk_params()  local
4801 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_calculate_sclk_params()
4802 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_calculate_sclk_params()
4803 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_calculate_sclk_params()
4804 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_calculate_sclk_params()
4805 	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;  in si_calculate_sclk_params()
4806 	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
4893 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mclk_value()  local
4894 	u32  dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_mclk_value()
4895 	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_mclk_value()
4896 	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_mclk_value()
4897 	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_mclk_value()
4898 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_mclk_value()
4899 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_mclk_value()
4900 	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_mclk_value()
4901 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;  in si_populate_mclk_value()
4902 	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;  in si_populate_mclk_value()
4995 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_level_to_smc()  local
5002 	    (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))  in si_convert_power_level_to_smc()
5003 		level->gen2PCIE = (u8)si_pi->force_pcie_gen;  in si_convert_power_level_to_smc()
5080 	if (si_pi->vddc_phase_shed_control) {  in si_convert_power_level_to_smc()
5091 	level->MaxPoweredUpCU = si_pi->max_cu;  in si_convert_power_level_to_smc()
5149 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_disable_ulv()  local
5150 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()
5162 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_is_state_ulv_compatible()  local
5163 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()
5190 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_power_state_conditionally_enable_ulv()  local
5191 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()
5207 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_state_to_smc()  local
5232 			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {  in si_convert_power_state_to_smc()
5284 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_sw_state()  local
5287 	u32 address = si_pi->state_table_start +  in si_upload_sw_state()
5292 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()
5301 				   state_size, si_pi->sram_end);  in si_upload_sw_state()
5308 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_ulv_state()  local
5309 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()
5313 		u32 address = si_pi->state_table_start +  in si_upload_ulv_state()
5315 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()
5323 						   state_size, si_pi->sram_end);  in si_upload_ulv_state()
5547 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_mc_reg_table()  local
5549 	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;  in si_initialize_mc_reg_table()
5598 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_addresses()  local
5601 	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {  in si_populate_mc_reg_addresses()
5602 		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {  in si_populate_mc_reg_addresses()
5606 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);  in si_populate_mc_reg_addresses()
5608 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);  in si_populate_mc_reg_addresses()
5633 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_mc_reg_table_entry_to_smc()  local
5636 	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {  in si_convert_mc_reg_table_entry_to_smc()
5637 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in si_convert_mc_reg_table_entry_to_smc()
5641 	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))  in si_convert_mc_reg_table_entry_to_smc()
5644 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],  in si_convert_mc_reg_table_entry_to_smc()
5645 				mc_reg_table_data, si_pi->mc_reg_table.last,  in si_convert_mc_reg_table_entry_to_smc()
5646 				si_pi->mc_reg_table.valid_flag);  in si_convert_mc_reg_table_entry_to_smc()
5667 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_table()  local
5668 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()
5669 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_populate_mc_reg_table()
5680 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5682 				si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5683 				si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5689 		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5691 					si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5692 					si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5696 	return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,  in si_populate_mc_reg_table()
5698 				    sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);  in si_populate_mc_reg_table()
5705 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_mc_reg_table()  local
5706 	u32 address = si_pi->mc_reg_table_start +  in si_upload_mc_reg_table()
5709 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_upload_mc_reg_table()
5719 				    si_pi->sram_end);  in si_upload_mc_reg_table()
5760 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_request_link_speed_change_before_state_change()  local
5764 	if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)  in si_request_link_speed_change_before_state_change()
5767 		current_link_speed = si_pi->force_pcie_gen;  in si_request_link_speed_change_before_state_change()
5769 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_request_link_speed_change_before_state_change()
5770 	si_pi->pspp_notify_required = false;  in si_request_link_speed_change_before_state_change()
5777 			si_pi->force_pcie_gen = RADEON_PCIE_GEN2;  in si_request_link_speed_change_before_state_change()
5785 			si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);  in si_request_link_speed_change_before_state_change()
5790 			si_pi->pspp_notify_required = true;  in si_request_link_speed_change_before_state_change()
5798 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_notify_link_speed_change_after_state_change()  local
5802 	if (si_pi->pspp_notify_required) {  in si_notify_link_speed_change_after_state_change()
5841 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_max_cu_value()  local
5850 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5856 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5864 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5869 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5872 			si_pi->max_cu = 0;  in si_set_max_cu_value()
5876 		si_pi->max_cu = 0;  in si_set_max_cu_value()
6020 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_static_mode()  local
6023 	if (si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_static_mode()
6025 		si_pi->fan_ctrl_default_mode = tmp;  in si_fan_ctrl_set_static_mode()
6027 		si_pi->t_min = tmp;  in si_fan_ctrl_set_static_mode()
6028 		si_pi->fan_ctrl_is_in_default_mode = false;  in si_fan_ctrl_set_static_mode()
6042 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_thermal_setup_fan_table()  local
6051 	if (!si_pi->fan_table_start) {  in si_thermal_setup_fan_table()
6104 				   si_pi->fan_table_start,  in si_thermal_setup_fan_table()
6107 				   si_pi->sram_end);  in si_thermal_setup_fan_table()
6119 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_start_smc_fan_control()  local
6124 		si_pi->fan_is_controlled_by_smc = true;  in si_fan_ctrl_start_smc_fan_control()
6133 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_stop_smc_fan_control()  local
6139 		si_pi->fan_is_controlled_by_smc = false;  in si_fan_ctrl_stop_smc_fan_control()
6174 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_fan_speed_percent()  local
6182 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_set_fan_speed_percent()
6222 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_get_mode()  local
6225 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_get_mode()
6286 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_default_mode()  local
6289 	if (!si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_default_mode()
6291 		tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);  in si_fan_ctrl_set_default_mode()
6295 		tmp |= TMIN(si_pi->t_min);  in si_fan_ctrl_set_default_mode()
6297 		si_pi->fan_ctrl_is_in_default_mode = true;  in si_fan_ctrl_set_default_mode()
6363 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_dpm_enable()  local
6369 	if (pi->voltage_control || si_pi->voltage_control_svi2)  in si_dpm_enable()
6373 	if (pi->voltage_control || si_pi->voltage_control_svi2) {  in si_dpm_enable()
6748 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_parse_pplib_clock_info()  local
6765 						 si_pi->sys_pcie_mask,  in si_parse_pplib_clock_info()
6766 						 si_pi->boot_pcie_gen,  in si_parse_pplib_clock_info()
6778 		si_pi->acpi_pcie_gen = pl->pcie_gen;  in si_parse_pplib_clock_info()
6784 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
6785 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6786 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
6787 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
6788 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
6789 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()
6806 		si_pi->mvdd_bootup_value = mvdd;  in si_parse_pplib_clock_info()
6914 	struct si_power_info *si_pi;  in si_dpm_init()  local
6919 	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);  in si_dpm_init()
6920 	if (si_pi == NULL)  in si_dpm_init()
6922 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6923 	ni_pi = &si_pi->ni;  in si_dpm_init()
6929 		si_pi->sys_pcie_mask = 0;  in si_dpm_init()
6931 		si_pi->sys_pcie_mask = mask;  in si_dpm_init()
6932 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_dpm_init()
6933 	si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);  in si_dpm_init()
7002 		si_pi->voltage_control_svi2 =  in si_dpm_init()
7005 		if (si_pi->voltage_control_svi2)  in si_dpm_init()
7007 						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);  in si_dpm_init()
7018 		si_pi->vddci_control_svi2 =  in si_dpm_init()
7022 	si_pi->vddc_phase_shed_control =  in si_dpm_init()
7035 	si_pi->sclk_deep_sleep_above_low = false;  in si_dpm_init()
7052 	si_pi->sram_end = SMC_RAM_END;  in si_dpm_init()
7070 	si_pi->fan_ctrl_is_in_default_mode = true;  in si_dpm_init()