1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
2989 					struct radeon_ps *rps)  in si_apply_state_adjust_rules()  argument
2991 	struct ni_ps *ps = ni_get_ps(rps);  in si_apply_state_adjust_rules()
3019 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3020 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in si_apply_state_adjust_rules()
3021 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in si_apply_state_adjust_rules()
3022 		si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,  in si_apply_state_adjust_rules()
3025 		rps->evclk = 0;  in si_apply_state_adjust_rules()
3026 		rps->ecclk = 0;  in si_apply_state_adjust_rules()
3033 	if (rps->vclk || rps->dclk) {  in si_apply_state_adjust_rules()
3109 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3416 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()  local
3417 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_force_performance_level()
6717 					  struct radeon_ps *rps,  in si_parse_pplib_non_clock_info()  argument
6721 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in si_parse_pplib_non_clock_info()
6722 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in si_parse_pplib_non_clock_info()
6723 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in si_parse_pplib_non_clock_info()
6726 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in si_parse_pplib_non_clock_info()
6727 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in si_parse_pplib_non_clock_info()
6728 	} else if (r600_is_uvd_state(rps->class, rps->class2)) {  in si_parse_pplib_non_clock_info()
6729 		rps->vclk = RV770_DEFAULT_VCLK_FREQ;  in si_parse_pplib_non_clock_info()
6730 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in si_parse_pplib_non_clock_info()
6732 		rps->vclk = 0;  in si_parse_pplib_non_clock_info()
6733 		rps->dclk = 0;  in si_parse_pplib_non_clock_info()
6736 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in si_parse_pplib_non_clock_info()
6737 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6738 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in si_parse_pplib_non_clock_info()
6739 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6743 				      struct radeon_ps *rps, int index,  in si_parse_pplib_clock_info()  argument
6749 	struct ni_ps *ps = ni_get_ps(rps);  in si_parse_pplib_clock_info()
6775 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in si_parse_pplib_clock_info()
6781 	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&  in si_parse_pplib_clock_info()
6799 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in si_parse_pplib_clock_info()
6809 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==  in si_parse_pplib_clock_info()
7092 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_debugfs_print_current_performance_level()  local
7093 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_debugfs_print_current_performance_level()
7103 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in si_dpm_debugfs_print_current_performance_level()
7112 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_sclk()  local
7113 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_sclk()
7130 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_mclk()  local
7131 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_mclk()