Lines Matching refs:rdev
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev) in si_get_pi() argument
1765 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, in si_calculate_leakage_for_v_and_t() argument
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev, in si_calculate_leakage_for_v() argument
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev, in si_update_dte_from_pl2() argument
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev) in si_initialize_powertune_defaults() argument
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_powertune_defaults()
1869 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_powertune_defaults()
1872 if (rdev->family == CHIP_TAHITI) { in si_initialize_powertune_defaults()
1879 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1906 } else if (rdev->family == CHIP_PITCAIRN) { in si_initialize_powertune_defaults()
1907 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1943 } else if (rdev->family == CHIP_VERDE) { in si_initialize_powertune_defaults()
1948 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1994 } else if (rdev->family == CHIP_OLAND) { in si_initialize_powertune_defaults()
1995 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
2044 } else if (rdev->family == CHIP_HAINAN) { in si_initialize_powertune_defaults()
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) in si_get_smc_power_scaling_factor() argument
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) in si_calculate_cac_wintime() argument
2103 xclk = radeon_get_xclk(rdev); in si_calculate_cac_wintime()
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, in si_calculate_adjusted_tdp_limits() argument
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, in si_populate_smc_tdp_limits() argument
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits()
2158 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits()
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits()
2174 ret = si_calculate_adjusted_tdp_limits(rdev, in si_populate_smc_tdp_limits()
2176 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2189 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits()
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, in si_populate_smc_tdp_limits_2() argument
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2223 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits_2()
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2235 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2237 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits_2()
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, in si_calculate_power_efficiency_ratio() argument
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, in si_should_disable_uvd_powertune() argument
2276 struct si_power_info *si_pi = si_get_pi(rdev); in si_should_disable_uvd_powertune()
2285 static int si_populate_power_containment_values(struct radeon_device *rdev, in si_populate_power_containment_values() argument
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_power_containment_values()
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_power_containment_values()
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); in si_populate_power_containment_values()
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, in si_populate_power_containment_values()
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev, in si_populate_sq_ramping_values() argument
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_sq_ramping_values()
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2436 static int si_enable_power_containment(struct radeon_device *rdev, in si_enable_power_containment() argument
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_power_containment()
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_power_containment()
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); in si_enable_power_containment()
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); in si_enable_power_containment()
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) in si_initialize_smc_dte_tables() argument
2468 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_dte_tables()
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, in si_initialize_smc_dte_tables()
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, in si_get_cac_std_voltage_max_min() argument
2534 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_cac_std_voltage_max_min()
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev, in si_init_dte_leakage_table() argument
2581 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_dte_leakage_table()
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_dte_leakage_table()
2597 si_calculate_leakage_for_v_and_t(rdev, in si_init_dte_leakage_table()
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev, in si_init_simplified_leakage_table() argument
2620 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_simplified_leakage_table()
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_simplified_leakage_table()
2632 si_calculate_leakage_for_v(rdev, in si_init_simplified_leakage_table()
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) in si_initialize_smc_cac_tables() argument
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_smc_cac_tables()
2654 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_cac_tables()
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; in si_initialize_smc_cac_tables()
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); in si_initialize_smc_cac_tables()
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); in si_initialize_smc_cac_tables()
2691 ret = si_init_dte_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, in si_initialize_smc_cac_tables()
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); in si_initialize_smc_cac_tables()
2735 static int si_program_cac_config_registers(struct radeon_device *rdev, in si_program_cac_config_registers() argument
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) in si_initialize_hardware_cac_manager() argument
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_hardware_cac_manager()
2777 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_hardware_cac_manager()
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2797 static int si_enable_smc_cac(struct radeon_device *rdev, in si_enable_smc_cac() argument
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_smc_cac()
2802 struct si_power_info *si_pi = si_get_pi(rdev); in si_enable_smc_cac()
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_smc_cac()
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); in si_enable_smc_cac()
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); in si_enable_smc_cac()
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); in si_enable_smc_cac()
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); in si_enable_smc_cac()
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); in si_enable_smc_cac()
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); in si_enable_smc_cac()
2844 static int si_init_smc_spll_table(struct radeon_device *rdev) in si_init_smc_spll_table() argument
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_init_smc_spll_table()
2847 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_spll_table()
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, in si_init_smc_spll_table()
2938 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, in si_get_lower_of_leakage_and_vce_voltage() argument
2942 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_lower_of_leakage_and_vce_voltage()
2956 static int si_get_vce_clock_voltage(struct radeon_device *rdev, in si_get_vce_clock_voltage() argument
2962 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
2983 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); in si_get_vce_clock_voltage()
2988 static void si_apply_state_adjust_rules(struct radeon_device *rdev, in si_apply_state_adjust_rules() argument
3004 if (rdev->pdev->vendor == p->chip_vendor && in si_apply_state_adjust_rules()
3005 rdev->pdev->device == p->chip_device && in si_apply_state_adjust_rules()
3006 rdev->pdev->subsystem_vendor == p->subsys_vendor && in si_apply_state_adjust_rules()
3007 rdev->pdev->subsystem_device == p->subsys_device) { in si_apply_state_adjust_rules()
3015 if (rdev->pdev->device == 0x6811 && in si_apply_state_adjust_rules()
3016 rdev->pdev->revision == 0x81) in si_apply_state_adjust_rules()
3020 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3021 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3022 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3029 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
3030 ni_dpm_vblank_too_short(rdev)) in si_apply_state_adjust_rules()
3038 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
3039 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3041 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3047 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
3061 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3063 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3065 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3110 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3111 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3112 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3113 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3161 btc_adjust_clock_combinations(rdev, max_limits, in si_apply_state_adjust_rules()
3167 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3170 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3173 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3176 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3177 rdev->clock.current_dispclk, in si_apply_state_adjust_rules()
3182 btc_apply_voltage_delta_rules(rdev, in si_apply_state_adjust_rules()
3190 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3196 static int si_read_smc_soft_register(struct radeon_device *rdev,
3199 struct si_power_info *si_pi = si_get_pi(rdev);
3201 return si_read_smc_sram_dword(rdev,
3207 static int si_write_smc_soft_register(struct radeon_device *rdev, in si_write_smc_soft_register() argument
3210 struct si_power_info *si_pi = si_get_pi(rdev); in si_write_smc_soft_register()
3212 return si_write_smc_sram_dword(rdev, in si_write_smc_soft_register()
3217 static bool si_is_special_1gb_platform(struct radeon_device *rdev) in si_is_special_1gb_platform() argument
3238 if ((rdev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3245 static void si_get_leakage_vddc(struct radeon_device *rdev) in si_get_leakage_vddc() argument
3247 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_vddc()
3252 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3264 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, in si_get_leakage_voltage_from_leakage_index() argument
3267 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_voltage_from_leakage_index()
3291 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in si_set_dpm_event_sources() argument
3293 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_dpm_event_sources()
3326 static void si_enable_auto_throttle_source(struct radeon_device *rdev, in si_enable_auto_throttle_source() argument
3330 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_auto_throttle_source()
3335 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3340 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3345 static void si_start_dpm(struct radeon_device *rdev) in si_start_dpm() argument
3350 static void si_stop_dpm(struct radeon_device *rdev) in si_stop_dpm() argument
3355 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) in si_enable_sclk_control() argument
3365 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3371 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3380 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3382 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3387 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3390 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3397 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, in si_send_msg_to_smc_with_parameter() argument
3401 return si_send_msg_to_smc(rdev, msg); in si_send_msg_to_smc_with_parameter()
3404 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) in si_restrict_performance_levels_before_switch() argument
3406 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) in si_restrict_performance_levels_before_switch()
3409 …return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK)… in si_restrict_performance_levels_before_switch()
3413 int si_dpm_force_performance_level(struct radeon_device *rdev, in si_dpm_force_performance_level() argument
3416 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3421 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3424 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3427 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3430 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3433 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3436 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3440 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3446 static int si_set_boot_state(struct radeon_device *rdev)
3448 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3453 static int si_set_sw_state(struct radeon_device *rdev) in si_set_sw_state() argument
3455 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? in si_set_sw_state()
3459 static int si_halt_smc(struct radeon_device *rdev) in si_halt_smc() argument
3461 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) in si_halt_smc()
3464 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? in si_halt_smc()
3468 static int si_resume_smc(struct radeon_device *rdev) in si_resume_smc() argument
3470 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) in si_resume_smc()
3473 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? in si_resume_smc()
3477 static void si_dpm_start_smc(struct radeon_device *rdev) in si_dpm_start_smc() argument
3479 si_program_jump_on_start(rdev); in si_dpm_start_smc()
3480 si_start_smc(rdev); in si_dpm_start_smc()
3481 si_start_smc_clock(rdev); in si_dpm_start_smc()
3484 static void si_dpm_stop_smc(struct radeon_device *rdev) in si_dpm_stop_smc() argument
3486 si_reset_smc(rdev); in si_dpm_stop_smc()
3487 si_stop_smc_clock(rdev); in si_dpm_stop_smc()
3490 static int si_process_firmware_header(struct radeon_device *rdev) in si_process_firmware_header() argument
3492 struct si_power_info *si_pi = si_get_pi(rdev); in si_process_firmware_header()
3496 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3505 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3514 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3523 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3532 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3541 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3550 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3559 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3568 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3580 static void si_read_clock_registers(struct radeon_device *rdev) in si_read_clock_registers() argument
3582 struct si_power_info *si_pi = si_get_pi(rdev); in si_read_clock_registers()
3601 static void si_enable_thermal_protection(struct radeon_device *rdev, in si_enable_thermal_protection() argument
3610 static void si_enable_acpi_power_management(struct radeon_device *rdev) in si_enable_acpi_power_management() argument
3616 static int si_enter_ulp_state(struct radeon_device *rdev)
3625 static int si_exit_ulp_state(struct radeon_device *rdev)
3633 for (i = 0; i < rdev->usec_timeout; i++) {
3643 static int si_notify_smc_display_change(struct radeon_device *rdev, in si_notify_smc_display_change() argument
3649 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? in si_notify_smc_display_change()
3653 static void si_program_response_times(struct radeon_device *rdev) in si_program_response_times() argument
3659 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); in si_program_response_times()
3661 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3662 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; in si_program_response_times()
3670 reference_clock = radeon_get_xclk(rdev); in si_program_response_times()
3676 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); in si_program_response_times()
3677 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); in si_program_response_times()
3678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); in si_program_response_times()
3679 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); in si_program_response_times()
3682 static void si_program_ds_registers(struct radeon_device *rdev) in si_program_ds_registers() argument
3684 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_program_ds_registers()
3694 static void si_program_display_gap(struct radeon_device *rdev) in si_program_display_gap() argument
3700 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3705 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3715 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3716 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3718 for (i = 0; i < rdev->num_crtc; i++) { in si_program_display_gap()
3719 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3722 if (i == rdev->num_crtc) in si_program_display_gap()
3736 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3739 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) in si_enable_spread_spectrum() argument
3741 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_spread_spectrum()
3752 static void si_setup_bsp(struct radeon_device *rdev) in si_setup_bsp() argument
3754 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_setup_bsp()
3755 u32 xclk = radeon_get_xclk(rdev); in si_setup_bsp()
3776 static void si_program_git(struct radeon_device *rdev) in si_program_git() argument
3781 static void si_program_tp(struct radeon_device *rdev) in si_program_tp() argument
3801 static void si_program_tpp(struct radeon_device *rdev) in si_program_tpp() argument
3806 static void si_program_sstp(struct radeon_device *rdev) in si_program_sstp() argument
3811 static void si_enable_display_gap(struct radeon_device *rdev) in si_enable_display_gap() argument
3825 static void si_program_vc(struct radeon_device *rdev) in si_program_vc() argument
3827 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_program_vc()
3832 static void si_clear_vc(struct radeon_device *rdev) in si_clear_vc() argument
3872 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3874 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_strobe_mode_settings()
3892 static int si_upload_firmware(struct radeon_device *rdev) in si_upload_firmware() argument
3894 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_firmware()
3897 si_reset_smc(rdev); in si_upload_firmware()
3898 si_stop_smc_clock(rdev); in si_upload_firmware()
3900 ret = si_load_smc_ucode(rdev, si_pi->sram_end); in si_upload_firmware()
3905 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, in si_validate_phase_shedding_tables() argument
3932 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, in si_trim_voltage_table_to_fit_state_table() argument
3949 static int si_get_svi2_voltage_table(struct radeon_device *rdev, in si_get_svi2_voltage_table() argument
3970 static int si_construct_voltage_tables(struct radeon_device *rdev) in si_construct_voltage_tables() argument
3972 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_construct_voltage_tables()
3973 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_construct_voltage_tables()
3974 struct si_power_info *si_pi = si_get_pi(rdev); in si_construct_voltage_tables()
3978 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
3984 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3988 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
3989 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3998 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, in si_construct_voltage_tables()
4004 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
4009 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
4010 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4017 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, in si_construct_voltage_tables()
4031 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
4037 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
4050 static void si_populate_smc_voltage_table(struct radeon_device *rdev, in si_populate_smc_voltage_table() argument
4060 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, in si_populate_smc_voltage_tables() argument
4063 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_voltage_tables()
4064 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_voltage_tables()
4065 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_voltage_tables()
4069 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, in si_populate_smc_voltage_tables()
4071 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, in si_populate_smc_voltage_tables()
4073 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, in si_populate_smc_voltage_tables()
4077 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); in si_populate_smc_voltage_tables()
4090 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); in si_populate_smc_voltage_tables()
4098 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4105 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4106 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4107 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4112 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, in si_populate_smc_voltage_tables()
4123 static int si_populate_voltage_value(struct radeon_device *rdev, in si_populate_voltage_value() argument
4143 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4146 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mvdd_value()
4147 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mvdd_value()
4160 static int si_get_std_voltage_value(struct radeon_device *rdev, in si_get_std_voltage_value() argument
4168 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4169 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4170 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4173 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4175 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4177 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4179 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4182 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4188 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4190 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4192 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4194 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4197 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4203 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4204 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4211 static int si_populate_std_voltage_value(struct radeon_device *rdev, in si_populate_std_voltage_value() argument
4221 static int si_populate_phase_shedding_value(struct radeon_device *rdev, in si_populate_phase_shedding_value() argument
4240 static int si_init_arb_table_index(struct radeon_device *rdev) in si_init_arb_table_index() argument
4242 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_arb_table_index()
4246 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); in si_init_arb_table_index()
4253 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); in si_init_arb_table_index()
4256 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) in si_initial_switch_from_arb_f0_to_f1() argument
4258 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); in si_initial_switch_from_arb_f0_to_f1()
4261 static int si_reset_to_default(struct radeon_device *rdev) in si_reset_to_default() argument
4263 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? in si_reset_to_default()
4267 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) in si_force_switch_to_arb_f0() argument
4269 struct si_power_info *si_pi = si_get_pi(rdev); in si_force_switch_to_arb_f0()
4273 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4283 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); in si_force_switch_to_arb_f0()
4286 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, in si_calculate_memory_refresh_rate() argument
4305 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, in si_populate_memory_timing_parameters() argument
4314 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); in si_populate_memory_timing_parameters()
4316 radeon_atom_set_engine_dram_timings(rdev, in si_populate_memory_timing_parameters()
4331 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, in si_do_program_memory_timing_parameters() argument
4335 struct si_power_info *si_pi = si_get_pi(rdev); in si_do_program_memory_timing_parameters()
4341 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4344 ret = si_copy_bytes_to_smc(rdev, in si_do_program_memory_timing_parameters()
4358 static int si_program_memory_timing_parameters(struct radeon_device *rdev, in si_program_memory_timing_parameters() argument
4361 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, in si_program_memory_timing_parameters()
4365 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, in si_populate_initial_mvdd_value() argument
4368 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_initial_mvdd_value()
4369 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_initial_mvdd_value()
4372 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4378 static int si_populate_smc_initial_state(struct radeon_device *rdev, in si_populate_smc_initial_state() argument
4383 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_initial_state()
4384 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_initial_state()
4385 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_initial_state()
4432 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_initial_state()
4439 ret = si_get_std_voltage_value(rdev, in si_populate_smc_initial_state()
4443 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_initial_state()
4449 si_populate_voltage_value(rdev, in si_populate_smc_initial_state()
4455 si_populate_phase_shedding_value(rdev, in si_populate_smc_initial_state()
4456 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4462 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); in si_populate_smc_initial_state()
4473 si_get_strobe_mode_settings(rdev, in si_populate_smc_initial_state()
4501 static int si_populate_smc_acpi_state(struct radeon_device *rdev, in si_populate_smc_acpi_state() argument
4504 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_acpi_state()
4505 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_acpi_state()
4506 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_acpi_state()
4526 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4531 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4534 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4541 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4542 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4549 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4554 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4558 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4562 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, in si_populate_smc_acpi_state()
4568 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4569 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4578 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_populate_smc_acpi_state()
4622 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); in si_populate_smc_acpi_state()
4642 static int si_populate_ulv_state(struct radeon_device *rdev, in si_populate_ulv_state() argument
4645 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_ulv_state()
4646 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_ulv_state()
4651 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, in si_populate_ulv_state()
4673 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) in si_program_ulv_memory_timing_parameters() argument
4675 struct si_power_info *si_pi = si_get_pi(rdev); in si_program_ulv_memory_timing_parameters()
4680 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
4685 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, in si_program_ulv_memory_timing_parameters()
4688 ret = si_copy_bytes_to_smc(rdev, in si_program_ulv_memory_timing_parameters()
4699 static void si_get_mvdd_configuration(struct radeon_device *rdev) in si_get_mvdd_configuration() argument
4701 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_mvdd_configuration()
4706 static int si_init_smc_table(struct radeon_device *rdev) in si_init_smc_table() argument
4708 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_init_smc_table()
4709 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_table()
4710 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4717 si_populate_smc_voltage_tables(rdev, table); in si_init_smc_table()
4719 switch (rdev->pm.int_thermal_type) { in si_init_smc_table()
4732 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4735 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4736 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) in si_init_smc_table()
4740 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4746 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4749 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4751 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
4752 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, in si_init_smc_table()
4756 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); in si_init_smc_table()
4760 ret = si_populate_smc_acpi_state(rdev, table); in si_init_smc_table()
4766 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, in si_init_smc_table()
4772 ret = si_populate_ulv_state(rdev, &table->ULVState); in si_init_smc_table()
4776 ret = si_program_ulv_memory_timing_parameters(rdev); in si_init_smc_table()
4783 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4784 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
4789 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, in si_init_smc_table()
4794 static int si_calculate_sclk_params(struct radeon_device *rdev, in si_calculate_sclk_params() argument
4798 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_calculate_sclk_params()
4799 struct si_power_info *si_pi = si_get_pi(rdev); in si_calculate_sclk_params()
4808 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
4813 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_calculate_sclk_params()
4839 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_calculate_sclk_params()
4864 static int si_populate_sclk_value(struct radeon_device *rdev, in si_populate_sclk_value() argument
4871 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
4885 static int si_populate_mclk_value(struct radeon_device *rdev, in si_populate_mclk_value() argument
4892 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mclk_value()
4893 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mclk_value()
4906 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in si_populate_mclk_value()
4930 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
4939 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_populate_mclk_value()
4974 static void si_populate_smc_sp(struct radeon_device *rdev, in si_populate_smc_sp() argument
4979 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_sp()
4989 static int si_convert_power_level_to_smc(struct radeon_device *rdev, in si_convert_power_level_to_smc() argument
4993 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_convert_power_level_to_smc()
4994 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_level_to_smc()
4995 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_level_to_smc()
5007 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
5017 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5031 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
5043 level->strobeMode = si_get_strobe_mode_settings(rdev, in si_convert_power_level_to_smc()
5049 ret = si_populate_mclk_value(rdev, in si_convert_power_level_to_smc()
5057 ret = si_populate_voltage_value(rdev, in si_convert_power_level_to_smc()
5064 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5068 ret = si_populate_std_voltage_value(rdev, std_vddc, in si_convert_power_level_to_smc()
5074 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_convert_power_level_to_smc()
5081 ret = si_populate_phase_shedding_value(rdev, in si_convert_power_level_to_smc()
5082 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5093 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5098 static int si_populate_smc_t(struct radeon_device *rdev, in si_populate_smc_t() argument
5102 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_t()
5147 static int si_disable_ulv(struct radeon_device *rdev) in si_disable_ulv() argument
5149 struct si_power_info *si_pi = si_get_pi(rdev); in si_disable_ulv()
5153 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? in si_disable_ulv()
5159 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, in si_is_state_ulv_compatible() argument
5162 const struct si_power_info *si_pi = si_get_pi(rdev); in si_is_state_ulv_compatible()
5172 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5173 if (rdev->clock.current_dispclk <= in si_is_state_ulv_compatible()
5174 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5176 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5187 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, in si_set_power_state_conditionally_enable_ulv() argument
5190 const struct si_power_info *si_pi = si_get_pi(rdev); in si_set_power_state_conditionally_enable_ulv()
5194 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) in si_set_power_state_conditionally_enable_ulv()
5195 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? in si_set_power_state_conditionally_enable_ulv()
5201 static int si_convert_power_state_to_smc(struct radeon_device *rdev, in si_convert_power_state_to_smc() argument
5205 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_state_to_smc()
5206 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_convert_power_state_to_smc()
5207 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_state_to_smc()
5240 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5264 si_write_smc_soft_register(rdev, in si_convert_power_state_to_smc()
5268 si_populate_smc_sp(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5270 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5274 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5278 return si_populate_smc_t(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5281 static int si_upload_sw_state(struct radeon_device *rdev, in si_upload_sw_state() argument
5284 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_sw_state()
5296 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); in si_upload_sw_state()
5300 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_sw_state()
5306 static int si_upload_ulv_state(struct radeon_device *rdev) in si_upload_ulv_state() argument
5308 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_ulv_state()
5320 ret = si_populate_ulv_state(rdev, smc_state); in si_upload_ulv_state()
5322 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_ulv_state()
5329 static int si_upload_smc_data(struct radeon_device *rdev) in si_upload_smc_data() argument
5334 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5337 for (i = 0; i < rdev->num_crtc; i++) { in si_upload_smc_data()
5338 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5339 radeon_crtc = rdev->mode_info.crtcs[i]; in si_upload_smc_data()
5350 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5355 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5360 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5368 static int si_set_mc_special_registers(struct radeon_device *rdev, in si_set_mc_special_registers() argument
5371 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_mc_special_registers()
5545 static int si_initialize_mc_reg_table(struct radeon_device *rdev) in si_initialize_mc_reg_table() argument
5547 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_mc_reg_table()
5550 u8 module_index = rv770_get_memory_module_index(rdev); in si_initialize_mc_reg_table()
5572 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in si_initialize_mc_reg_table()
5582 ret = si_set_mc_special_registers(rdev, si_table); in si_initialize_mc_reg_table()
5595 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, in si_populate_mc_reg_addresses() argument
5598 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_addresses()
5629 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_entry_to_smc() argument
5633 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_mc_reg_table_entry_to_smc()
5649 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_to_smc() argument
5657 si_convert_mc_reg_table_entry_to_smc(rdev, in si_convert_mc_reg_table_to_smc()
5663 static int si_populate_mc_reg_table(struct radeon_device *rdev, in si_populate_mc_reg_table() argument
5667 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_table()
5673 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); in si_populate_mc_reg_table()
5675 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); in si_populate_mc_reg_table()
5677 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
5686 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, in si_populate_mc_reg_table()
5694 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); in si_populate_mc_reg_table()
5696 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
5701 static int si_upload_mc_reg_table(struct radeon_device *rdev, in si_upload_mc_reg_table() argument
5705 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_mc_reg_table()
5713 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); in si_upload_mc_reg_table()
5716 return si_copy_bytes_to_smc(rdev, address, in si_upload_mc_reg_table()
5723 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) in si_enable_voltage_control() argument
5731 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, in si_get_maximum_link_speed() argument
5746 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) in si_get_current_pcie_speed() argument
5756 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, in si_request_link_speed_change_before_state_change() argument
5760 struct si_power_info *si_pi = si_get_pi(rdev); in si_request_link_speed_change_before_state_change()
5761 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_request_link_speed_change_before_state_change()
5765 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); in si_request_link_speed_change_before_state_change()
5775 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in si_request_link_speed_change_before_state_change()
5781 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in si_request_link_speed_change_before_state_change()
5785 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); in si_request_link_speed_change_before_state_change()
5794 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, in si_notify_link_speed_change_after_state_change() argument
5798 struct si_power_info *si_pi = si_get_pi(rdev); in si_notify_link_speed_change_after_state_change()
5799 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_notify_link_speed_change_after_state_change()
5811 (si_get_current_pcie_speed(rdev) > 0)) in si_notify_link_speed_change_after_state_change()
5815 radeon_acpi_pcie_performance_request(rdev, request, false); in si_notify_link_speed_change_after_state_change()
5821 static int si_ds_request(struct radeon_device *rdev,
5824 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5828 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5832 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5839 static void si_set_max_cu_value(struct radeon_device *rdev) in si_set_max_cu_value() argument
5841 struct si_power_info *si_pi = si_get_pi(rdev); in si_set_max_cu_value()
5843 if (rdev->family == CHIP_VERDE) { in si_set_max_cu_value()
5844 switch (rdev->pdev->device) { in si_set_max_cu_value()
5880 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, in si_patch_single_dependency_table_based_on_leakage() argument
5889 switch (si_get_leakage_voltage_from_leakage_index(rdev, in si_patch_single_dependency_table_based_on_leakage()
5911 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) in si_patch_dependency_tables_based_on_leakage() argument
5915 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5916 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5917 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5918 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5919 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5920 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5924 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, in si_set_pcie_lane_width_in_smc() argument
5935 radeon_set_pcie_lanes(rdev, new_lane_width); in si_set_pcie_lane_width_in_smc()
5936 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5937 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
5941 static void si_set_vce_clock(struct radeon_device *rdev, in si_set_vce_clock() argument
5949 vce_v1_0_enable_mgcg(rdev, false); in si_set_vce_clock()
5951 vce_v1_0_enable_mgcg(rdev, true); in si_set_vce_clock()
5952 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
5956 void si_dpm_setup_asic(struct radeon_device *rdev) in si_dpm_setup_asic() argument
5960 r = si_mc_load_microcode(rdev); in si_dpm_setup_asic()
5963 rv770_get_memory_type(rdev); in si_dpm_setup_asic()
5964 si_read_clock_registers(rdev); in si_dpm_setup_asic()
5965 si_enable_acpi_power_management(rdev); in si_dpm_setup_asic()
5968 static int si_thermal_enable_alert(struct radeon_device *rdev, in si_thermal_enable_alert() argument
5978 rdev->irq.dpm_thermal = false; in si_thermal_enable_alert()
5979 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); in si_thermal_enable_alert()
5987 rdev->irq.dpm_thermal = true; in si_thermal_enable_alert()
5993 static int si_thermal_set_temperature_range(struct radeon_device *rdev, in si_thermal_set_temperature_range() argument
6012 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
6013 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
6018 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_static_mode() argument
6020 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_static_mode()
6040 static int si_thermal_setup_fan_table(struct radeon_device *rdev) in si_thermal_setup_fan_table() argument
6042 struct si_power_info *si_pi = si_get_pi(rdev); in si_thermal_setup_fan_table()
6052 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6059 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6063 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6067 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6068 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6070 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6071 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6076 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6077 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6078 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6085 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6093 reference_clock = radeon_get_xclk(rdev); in si_thermal_setup_fan_table()
6095 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6103 ret = si_copy_bytes_to_smc(rdev, in si_thermal_setup_fan_table()
6111 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6117 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_start_smc_fan_control() argument
6119 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_start_smc_fan_control()
6122 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); in si_fan_ctrl_start_smc_fan_control()
6131 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_stop_smc_fan_control() argument
6133 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_stop_smc_fan_control()
6136 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); in si_fan_ctrl_stop_smc_fan_control()
6146 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_get_fan_speed_percent() argument
6152 if (rdev->pm.no_fan) in si_fan_ctrl_get_fan_speed_percent()
6171 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_set_fan_speed_percent() argument
6174 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_fan_speed_percent()
6179 if (rdev->pm.no_fan) in si_fan_ctrl_set_fan_speed_percent()
6204 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_mode() argument
6208 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6209 si_fan_ctrl_stop_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6210 si_fan_ctrl_set_static_mode(rdev, mode); in si_fan_ctrl_set_mode()
6213 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6214 si_thermal_start_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6216 si_fan_ctrl_set_default_mode(rdev); in si_fan_ctrl_set_mode()
6220 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) in si_fan_ctrl_get_mode() argument
6222 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_get_mode()
6233 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6237 u32 xclk = radeon_get_xclk(rdev);
6239 if (rdev->pm.no_fan)
6242 if (rdev->pm.fan_pulses_per_revolution == 0)
6254 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6258 u32 xclk = radeon_get_xclk(rdev);
6260 if (rdev->pm.no_fan)
6263 if (rdev->pm.fan_pulses_per_revolution == 0)
6266 if ((speed < rdev->pm.fan_min_rpm) ||
6267 (speed > rdev->pm.fan_max_rpm))
6270 if (rdev->pm.dpm.fan.ucode_fan_control)
6271 si_fan_ctrl_stop_smc_fan_control(rdev);
6278 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6284 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) in si_fan_ctrl_set_default_mode() argument
6286 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_default_mode()
6301 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) in si_thermal_start_smc_fan_control() argument
6303 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6304 si_fan_ctrl_start_smc_fan_control(rdev); in si_thermal_start_smc_fan_control()
6305 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); in si_thermal_start_smc_fan_control()
6309 static void si_thermal_initialize(struct radeon_device *rdev) in si_thermal_initialize() argument
6313 if (rdev->pm.fan_pulses_per_revolution) { in si_thermal_initialize()
6315 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); in si_thermal_initialize()
6324 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) in si_thermal_start_thermal_controller() argument
6328 si_thermal_initialize(rdev); in si_thermal_start_thermal_controller()
6329 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_thermal_start_thermal_controller()
6332 ret = si_thermal_enable_alert(rdev, true); in si_thermal_start_thermal_controller()
6335 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6336 ret = si_halt_smc(rdev); in si_thermal_start_thermal_controller()
6339 ret = si_thermal_setup_fan_table(rdev); in si_thermal_start_thermal_controller()
6342 ret = si_resume_smc(rdev); in si_thermal_start_thermal_controller()
6345 si_thermal_start_smc_fan_control(rdev); in si_thermal_start_thermal_controller()
6351 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) in si_thermal_stop_thermal_controller() argument
6353 if (!rdev->pm.no_fan) { in si_thermal_stop_thermal_controller()
6354 si_fan_ctrl_set_default_mode(rdev); in si_thermal_stop_thermal_controller()
6355 si_fan_ctrl_stop_smc_fan_control(rdev); in si_thermal_stop_thermal_controller()
6359 int si_dpm_enable(struct radeon_device *rdev) in si_dpm_enable() argument
6361 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_enable()
6362 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_enable()
6363 struct si_power_info *si_pi = si_get_pi(rdev); in si_dpm_enable()
6364 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6367 if (si_is_smc_running(rdev)) in si_dpm_enable()
6370 si_enable_voltage_control(rdev, true); in si_dpm_enable()
6372 si_get_mvdd_configuration(rdev); in si_dpm_enable()
6374 ret = si_construct_voltage_tables(rdev); in si_dpm_enable()
6381 ret = si_initialize_mc_reg_table(rdev); in si_dpm_enable()
6386 si_enable_spread_spectrum(rdev, true); in si_dpm_enable()
6388 si_enable_thermal_protection(rdev, true); in si_dpm_enable()
6389 si_setup_bsp(rdev); in si_dpm_enable()
6390 si_program_git(rdev); in si_dpm_enable()
6391 si_program_tp(rdev); in si_dpm_enable()
6392 si_program_tpp(rdev); in si_dpm_enable()
6393 si_program_sstp(rdev); in si_dpm_enable()
6394 si_enable_display_gap(rdev); in si_dpm_enable()
6395 si_program_vc(rdev); in si_dpm_enable()
6396 ret = si_upload_firmware(rdev); in si_dpm_enable()
6401 ret = si_process_firmware_header(rdev); in si_dpm_enable()
6406 ret = si_initial_switch_from_arb_f0_to_f1(rdev); in si_dpm_enable()
6411 ret = si_init_smc_table(rdev); in si_dpm_enable()
6416 ret = si_init_smc_spll_table(rdev); in si_dpm_enable()
6421 ret = si_init_arb_table_index(rdev); in si_dpm_enable()
6427 ret = si_populate_mc_reg_table(rdev, boot_ps); in si_dpm_enable()
6433 ret = si_initialize_smc_cac_tables(rdev); in si_dpm_enable()
6438 ret = si_initialize_hardware_cac_manager(rdev); in si_dpm_enable()
6443 ret = si_initialize_smc_dte_tables(rdev); in si_dpm_enable()
6448 ret = si_populate_smc_tdp_limits(rdev, boot_ps); in si_dpm_enable()
6453 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); in si_dpm_enable()
6458 si_program_response_times(rdev); in si_dpm_enable()
6459 si_program_ds_registers(rdev); in si_dpm_enable()
6460 si_dpm_start_smc(rdev); in si_dpm_enable()
6461 ret = si_notify_smc_display_change(rdev, false); in si_dpm_enable()
6466 si_enable_sclk_control(rdev, true); in si_dpm_enable()
6467 si_start_dpm(rdev); in si_dpm_enable()
6469 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in si_dpm_enable()
6471 si_thermal_start_thermal_controller(rdev); in si_dpm_enable()
6473 ni_update_current_ps(rdev, boot_ps); in si_dpm_enable()
6478 static int si_set_temperature_range(struct radeon_device *rdev) in si_set_temperature_range() argument
6482 ret = si_thermal_enable_alert(rdev, false); in si_set_temperature_range()
6485 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_set_temperature_range()
6488 ret = si_thermal_enable_alert(rdev, true); in si_set_temperature_range()
6495 int si_dpm_late_enable(struct radeon_device *rdev) in si_dpm_late_enable() argument
6499 ret = si_set_temperature_range(rdev); in si_dpm_late_enable()
6506 void si_dpm_disable(struct radeon_device *rdev) in si_dpm_disable() argument
6508 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_disable()
6509 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6511 if (!si_is_smc_running(rdev)) in si_dpm_disable()
6513 si_thermal_stop_thermal_controller(rdev); in si_dpm_disable()
6514 si_disable_ulv(rdev); in si_dpm_disable()
6515 si_clear_vc(rdev); in si_dpm_disable()
6517 si_enable_thermal_protection(rdev, false); in si_dpm_disable()
6518 si_enable_power_containment(rdev, boot_ps, false); in si_dpm_disable()
6519 si_enable_smc_cac(rdev, boot_ps, false); in si_dpm_disable()
6520 si_enable_spread_spectrum(rdev, false); in si_dpm_disable()
6521 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); in si_dpm_disable()
6522 si_stop_dpm(rdev); in si_dpm_disable()
6523 si_reset_to_default(rdev); in si_dpm_disable()
6524 si_dpm_stop_smc(rdev); in si_dpm_disable()
6525 si_force_switch_to_arb_f0(rdev); in si_dpm_disable()
6527 ni_update_current_ps(rdev, boot_ps); in si_dpm_disable()
6530 int si_dpm_pre_set_power_state(struct radeon_device *rdev) in si_dpm_pre_set_power_state() argument
6532 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_pre_set_power_state()
6533 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6536 ni_update_requested_ps(rdev, new_ps); in si_dpm_pre_set_power_state()
6538 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); in si_dpm_pre_set_power_state()
6543 static int si_power_control_set_level(struct radeon_device *rdev) in si_power_control_set_level() argument
6545 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6548 ret = si_restrict_performance_levels_before_switch(rdev); in si_power_control_set_level()
6551 ret = si_halt_smc(rdev); in si_power_control_set_level()
6554 ret = si_populate_smc_tdp_limits(rdev, new_ps); in si_power_control_set_level()
6557 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); in si_power_control_set_level()
6560 ret = si_resume_smc(rdev); in si_power_control_set_level()
6563 ret = si_set_sw_state(rdev); in si_power_control_set_level()
6569 int si_dpm_set_power_state(struct radeon_device *rdev) in si_dpm_set_power_state() argument
6571 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_set_power_state()
6576 ret = si_disable_ulv(rdev); in si_dpm_set_power_state()
6581 ret = si_restrict_performance_levels_before_switch(rdev); in si_dpm_set_power_state()
6587 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6588 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6589 ret = si_enable_power_containment(rdev, new_ps, false); in si_dpm_set_power_state()
6594 ret = si_enable_smc_cac(rdev, new_ps, false); in si_dpm_set_power_state()
6599 ret = si_halt_smc(rdev); in si_dpm_set_power_state()
6604 ret = si_upload_sw_state(rdev, new_ps); in si_dpm_set_power_state()
6609 ret = si_upload_smc_data(rdev); in si_dpm_set_power_state()
6614 ret = si_upload_ulv_state(rdev); in si_dpm_set_power_state()
6620 ret = si_upload_mc_reg_table(rdev, new_ps); in si_dpm_set_power_state()
6626 ret = si_program_memory_timing_parameters(rdev, new_ps); in si_dpm_set_power_state()
6631 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6633 ret = si_resume_smc(rdev); in si_dpm_set_power_state()
6638 ret = si_set_sw_state(rdev); in si_dpm_set_power_state()
6643 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6644 si_set_vce_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6646 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6647 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); in si_dpm_set_power_state()
6652 ret = si_enable_smc_cac(rdev, new_ps, true); in si_dpm_set_power_state()
6657 ret = si_enable_power_containment(rdev, new_ps, true); in si_dpm_set_power_state()
6663 ret = si_power_control_set_level(rdev); in si_dpm_set_power_state()
6672 void si_dpm_post_set_power_state(struct radeon_device *rdev) in si_dpm_post_set_power_state() argument
6674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_post_set_power_state()
6677 ni_update_current_ps(rdev, new_ps); in si_dpm_post_set_power_state()
6681 void si_dpm_reset_asic(struct radeon_device *rdev)
6683 si_restrict_performance_levels_before_switch(rdev);
6684 si_disable_ulv(rdev);
6685 si_set_boot_state(rdev);
6689 void si_dpm_display_configuration_changed(struct radeon_device *rdev) in si_dpm_display_configuration_changed() argument
6691 si_program_display_gap(rdev); in si_dpm_display_configuration_changed()
6716 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, in si_parse_pplib_non_clock_info() argument
6737 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6739 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6742 static void si_parse_pplib_clock_info(struct radeon_device *rdev, in si_parse_pplib_clock_info() argument
6746 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_parse_pplib_clock_info()
6747 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_parse_pplib_clock_info()
6748 struct si_power_info *si_pi = si_get_pi(rdev); in si_parse_pplib_clock_info()
6764 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in si_parse_pplib_clock_info()
6770 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6801 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6802 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6803 pl->sclk = rdev->clock.default_sclk; in si_parse_pplib_clock_info()
6811 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6812 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6813 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6814 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6818 static int si_parse_power_table(struct radeon_device *rdev) in si_parse_power_table() argument
6820 struct radeon_mode_info *mode_info = &rdev->mode_info; in si_parse_power_table()
6850 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in si_parse_power_table()
6852 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6861 if (!rdev->pm.power_state[i].clock_info) in si_parse_power_table()
6865 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6868 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6869 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6883 si_parse_pplib_clock_info(rdev, in si_parse_power_table()
6884 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6890 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6895 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
6902 rdev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
6903 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
6909 int si_dpm_init(struct radeon_device *rdev) in si_dpm_init() argument
6922 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6927 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); in si_dpm_init()
6933 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); in si_dpm_init()
6935 si_set_max_cu_value(rdev); in si_dpm_init()
6937 rv770_get_max_vddc(rdev); in si_dpm_init()
6938 si_get_leakage_vddc(rdev); in si_dpm_init()
6939 si_patch_dependency_tables_based_on_leakage(rdev); in si_dpm_init()
6946 ret = r600_get_platform_caps(rdev); in si_dpm_init()
6950 ret = r600_parse_extended_power_table(rdev); in si_dpm_init()
6954 ret = si_parse_power_table(rdev); in si_dpm_init()
6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6960 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6961 r600_free_extended_power_table(rdev); in si_dpm_init()
6964 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6965 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6966 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6967 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6974 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6975 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6976 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6977 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
6979 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_dpm_init()
6989 if (si_is_special_1gb_platform(rdev)) in si_dpm_init()
6999 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
7006 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
7011 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, in si_dpm_init()
7015 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
7019 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
7023 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
7026 rv770_get_engine_memory_ss(rdev); in si_dpm_init()
7037 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in si_dpm_init()
7047 radeon_acpi_is_pcie_performance_request_supported(rdev); in si_dpm_init()
7054 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7055 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7056 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7057 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7058 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7059 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7060 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7062 si_initialize_powertune_defaults(rdev); in si_dpm_init()
7065 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7066 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7067 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7068 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7075 void si_dpm_fini(struct radeon_device *rdev) in si_dpm_fini() argument
7079 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7080 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7082 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
7083 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
7084 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7085 r600_free_extended_power_table(rdev); in si_dpm_fini()
7088 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in si_dpm_debugfs_print_current_performance_level() argument
7091 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_debugfs_print_current_performance_level()
7109 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) in si_dpm_get_current_sclk() argument
7111 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_sclk()
7127 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) in si_dpm_get_current_mclk() argument
7129 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_mclk()