1754 					 struct rv7xx_pl *pl,
4306 						struct rv7xx_pl *pl,  in si_populate_memory_timing_parameters()  argument
4314 		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);  in si_populate_memory_timing_parameters()
4317 					    pl->sclk,  in si_populate_memory_timing_parameters()
4318                                             pl->mclk);  in si_populate_memory_timing_parameters()
4651 	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,  in si_populate_ulv_state()
4680 	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,  in si_program_ulv_memory_timing_parameters()
4771 	if (ulv->supported && ulv->pl.vddc) {  in si_init_smc_table()
4990 					 struct rv7xx_pl *pl,  in si_convert_power_level_to_smc()  argument
5005 		level->gen2PCIE = (u8)pl->pcie_gen;  in si_convert_power_level_to_smc()
5007 	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in si_convert_power_level_to_smc()
5014 	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&  in si_convert_power_level_to_smc()
5025 		if (pl->mclk > pi->mclk_edc_enable_threshold)  in si_convert_power_level_to_smc()
5028 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)  in si_convert_power_level_to_smc()
5031 		level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);  in si_convert_power_level_to_smc()
5034 			if (si_get_mclk_frequency_ratio(pl->mclk, true) >=  in si_convert_power_level_to_smc()
5044 								pl->mclk);  in si_convert_power_level_to_smc()
5050 				     pl->sclk,  in si_convert_power_level_to_smc()
5051 				     pl->mclk,  in si_convert_power_level_to_smc()
5059 					pl->vddc, &level->vddc);  in si_convert_power_level_to_smc()
5075 						pl->vddci, &level->vddci);  in si_convert_power_level_to_smc()
5083 						       pl->vddc,  in si_convert_power_level_to_smc()
5084 						       pl->sclk,  in si_convert_power_level_to_smc()
5085 						       pl->mclk,  in si_convert_power_level_to_smc()
5093 	ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);  in si_convert_power_level_to_smc()
5167 	if (state->performance_levels[0].mclk != ulv->pl.mclk)  in si_is_state_ulv_compatible()
5175 			if (ulv->pl.vddc <  in si_is_state_ulv_compatible()
5312 	if (ulv->supported && ulv->pl.vddc) {  in si_upload_ulv_state()
5630 						 struct rv7xx_pl *pl,  in si_convert_mc_reg_table_entry_to_smc()  argument
5637 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in si_convert_mc_reg_table_entry_to_smc()
5685 	if (ulv->supported && ulv->pl.vddc != 0)  in si_populate_mc_reg_table()
5686 		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,  in si_populate_mc_reg_table()
6751 	struct rv7xx_pl *pl = &ps->performance_levels[index];  in si_parse_pplib_clock_info()  local
6756 	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);  in si_parse_pplib_clock_info()
6757 	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;  in si_parse_pplib_clock_info()
6758 	pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);  in si_parse_pplib_clock_info()
6759 	pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;  in si_parse_pplib_clock_info()
6761 	pl->vddc = le16_to_cpu(clock_info->si.usVDDC);  in si_parse_pplib_clock_info()
6762 	pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);  in si_parse_pplib_clock_info()
6763 	pl->flags = le32_to_cpu(clock_info->si.ulFlags);  in si_parse_pplib_clock_info()
6764 	pl->pcie_gen = r600_get_pcie_gen_support(rdev,  in si_parse_pplib_clock_info()
6770 	ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,  in si_parse_pplib_clock_info()
6773 		pl->vddc = leakage_voltage;  in si_parse_pplib_clock_info()
6776 		pi->acpi_vddc = pl->vddc;  in si_parse_pplib_clock_info()
6777 		eg_pi->acpi_vddci = pl->vddci;  in si_parse_pplib_clock_info()
6778 		si_pi->acpi_pcie_gen = pl->pcie_gen;  in si_parse_pplib_clock_info()
6785 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6792 	if (pi->min_vddc_in_table > pl->vddc)  in si_parse_pplib_clock_info()
6793 		pi->min_vddc_in_table = pl->vddc;  in si_parse_pplib_clock_info()
6795 	if (pi->max_vddc_in_table < pl->vddc)  in si_parse_pplib_clock_info()
6796 		pi->max_vddc_in_table = pl->vddc;  in si_parse_pplib_clock_info()
6802 		pl->mclk = rdev->clock.default_mclk;  in si_parse_pplib_clock_info()
6803 		pl->sclk = rdev->clock.default_sclk;  in si_parse_pplib_clock_info()
6804 		pl->vddc = vddc;  in si_parse_pplib_clock_info()
6805 		pl->vddci = vddci;  in si_parse_pplib_clock_info()
6811 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6812 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in si_parse_pplib_clock_info()
6813 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in si_parse_pplib_clock_info()
6814 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in si_parse_pplib_clock_info()
7094 	struct rv7xx_pl *pl;  in si_dpm_debugfs_print_current_performance_level()  local
7102 		pl = &ps->performance_levels[current_index];  in si_dpm_debugfs_print_current_performance_level()
7105 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);  in si_dpm_debugfs_print_current_performance_level()
7114 	struct rv7xx_pl *pl;  in si_dpm_get_current_sclk()  local
7122 		pl = &ps->performance_levels[current_index];  in si_dpm_get_current_sclk()
7123 		return pl->sclk;  in si_dpm_get_current_sclk()
7132 	struct rv7xx_pl *pl;  in si_dpm_get_current_mclk()  local
7140 		pl = &ps->performance_levels[current_index];  in si_dpm_get_current_mclk()
7141 		return pl->mclk;  in si_dpm_get_current_mclk()