Lines Matching refs:mclk
2995 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3049 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3050 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3074 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3075 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3078 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3079 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3082 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3083 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3094 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3097 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3112 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3113 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3118 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3142 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3144 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3145 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3148 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3153 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3154 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3171 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3174 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3872 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3878 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
3882 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); in si_get_strobe_mode_settings()
3884 result = si_get_ddr3_mclk_frequency_ratio(mclk); in si_get_strobe_mode_settings()
4143 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4150 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4223 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4231 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4318 pl->mclk); in si_populate_memory_timing_parameters()
4389 table->initialState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4391 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4393 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4395 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4397 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4399 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4401 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4403 table->initialState.levels[0].mclk.vMPLL_SS = in si_populate_smc_initial_state()
4405 table->initialState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4408 table->initialState.levels[0].mclk.mclk_value = in si_populate_smc_initial_state()
4409 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4459 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4474 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4476 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4591 table->ACPIState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
4593 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
4595 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
4597 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
4599 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4601 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
4603 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4605 table->ACPIState.levels[0].mclk.vMPLL_SS = in si_populate_smc_acpi_state()
4607 table->ACPIState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
4619 table->ACPIState.levels[0].mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4888 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value() argument
4960 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
4961 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
4962 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
4963 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
4964 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
4965 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
4966 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
4967 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
4968 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
4969 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
5014 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
5025 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
5028 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5031 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
5034 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5044 pl->mclk); in si_convert_power_level_to_smc()
5051 pl->mclk, in si_convert_power_level_to_smc()
5052 &level->mclk, in si_convert_power_level_to_smc()
5085 pl->mclk, in si_convert_power_level_to_smc()
5093 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5167 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5637 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6758 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
6759 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
6802 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6812 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6894 u32 sclk, mclk; in si_parse_power_table() local
6900 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
6901 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
6903 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7066 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7105 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7141 return pl->mclk; in si_dpm_get_current_mclk()