1765         struct si_power_info *pi = rdev->pm.dpm.priv;  in si_get_pi()
1839 	u32 p_limit1 = rdev->pm.dpm.tdp_limit;  in si_update_dte_from_pl2()
1840 	u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;  in si_update_dte_from_pl2()
2129 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in si_calculate_adjusted_tdp_limits()
2132 	max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2135 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2136 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in si_calculate_adjusted_tdp_limits()
2138 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2139 		adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;  in si_calculate_adjusted_tdp_limits()
2140 		if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)  in si_calculate_adjusted_tdp_limits()
2141 			*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;  in si_calculate_adjusted_tdp_limits()
2163 		struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;  in si_populate_smc_tdp_limits()
2176 						       rdev->pm.dpm.tdp_adjustment,  in si_populate_smc_tdp_limits()
2233 			cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);  in si_populate_smc_tdp_limits_2()
2235 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_…  in si_populate_smc_tdp_limits_2()
2395 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in si_populate_sq_ramping_values()
2417 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in si_populate_sq_ramping_values()
2536 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in si_get_cac_std_voltage_max_min()
2673 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2700 	load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;  in si_initialize_smc_cac_tables()
2962 		&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in si_get_vce_clock_voltage()
3020 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in si_apply_state_adjust_rules()
3021 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in si_apply_state_adjust_rules()
3029 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in si_apply_state_adjust_rules()
3038 	if (rdev->pm.dpm.ac_power)  in si_apply_state_adjust_rules()
3039 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_apply_state_adjust_rules()
3041 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in si_apply_state_adjust_rules()
3047 	if (rdev->pm.dpm.ac_power == false) {  in si_apply_state_adjust_rules()
3061 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
3063 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
3065 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3110 		if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)  in si_apply_state_adjust_rules()
3111 			sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;  in si_apply_state_adjust_rules()
3112 		if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)  in si_apply_state_adjust_rules()
3113 			mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;  in si_apply_state_adjust_rules()
3167 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
3170 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
3173 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3176 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in si_apply_state_adjust_rules()
3190 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in si_apply_state_adjust_rules()
3416 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()
3440 	rdev->pm.dpm.forced_level = level;  in si_dpm_force_performance_level()
3661 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in si_program_response_times()
3662         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;  in si_program_response_times()
3700 	if (rdev->pm.dpm.new_active_crtc_count > 0)  in si_program_display_gap()
3705 	if (rdev->pm.dpm.new_active_crtc_count > 1)  in si_program_display_gap()
3715 	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&  in si_program_display_gap()
3716 	    (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {  in si_program_display_gap()
3719 			if (rdev->pm.dpm.new_active_crtcs & (1 << i))  in si_program_display_gap()
3736 	si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);  in si_program_display_gap()
3989 						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_construct_voltage_tables()
4010 						&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_construct_voltage_tables()
4106 							      &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {  in si_populate_smc_voltage_tables()
4168 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {  in si_get_std_voltage_value()
4169 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {  in si_get_std_voltage_value()
4170 			if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)  in si_get_std_voltage_value()
4173 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4175 				    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4177 					if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4179 							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4182 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4188 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4190 					    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4192 						if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4194 								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4197 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4203 			if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4204 				*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in si_get_std_voltage_value()
4456 						 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_initial_state()
4542 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4569 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4710 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in si_init_smc_table()
4732 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in si_init_smc_table()
4735 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {  in si_init_smc_table()
4740 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in si_init_smc_table()
4746 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)  in si_init_smc_table()
4749 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {  in si_init_smc_table()
4751 		vr_hot_gpio = rdev->pm.dpm.backbias_response_time;  in si_init_smc_table()
5017 	    (rdev->pm.dpm.new_active_crtc_count <= 2)) {  in si_convert_power_level_to_smc()
5082 						       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_convert_power_level_to_smc()
5172 	for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {  in si_is_state_ulv_compatible()
5174 		    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {  in si_is_state_ulv_compatible()
5176 			    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)  in si_is_state_ulv_compatible()
5334 	if (rdev->pm.dpm.new_active_crtc_count == 0)  in si_upload_smc_data()
5338 		if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {  in si_upload_smc_data()
5916 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in si_patch_dependency_tables_based_on_leakage()
5918 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
5920 								&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
6012 	rdev->pm.dpm.thermal.min_temp = low_temp;  in si_thermal_set_temperature_range()
6013 	rdev->pm.dpm.thermal.max_temp = high_temp;  in si_thermal_set_temperature_range()
6052 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6059 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6063 	tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;  in si_thermal_setup_fan_table()
6067 	t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;  in si_thermal_setup_fan_table()
6068 	t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;  in si_thermal_setup_fan_table()
6070 	pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;  in si_thermal_setup_fan_table()
6071 	pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;  in si_thermal_setup_fan_table()
6076 	fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);  in si_thermal_setup_fan_table()
6077 	fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);  in si_thermal_setup_fan_table()
6078 	fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);  in si_thermal_setup_fan_table()
6085 	fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);  in si_thermal_setup_fan_table()
6095 	fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *  in si_thermal_setup_fan_table()
6111 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6208 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6213 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6270 	if (rdev->pm.dpm.fan.ucode_fan_control)
6303 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_smc_fan_control()
6335 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_thermal_controller()
6364 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_enable()
6509 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_disable()
6533 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in si_dpm_pre_set_power_state()
6545 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in si_power_control_set_level()
6737 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6739 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6811 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6812 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in si_parse_pplib_clock_info()
6813 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in si_parse_pplib_clock_info()
6814 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in si_parse_pplib_clock_info()
6850 	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *  in si_parse_power_table()
6852 	if (!rdev->pm.dpm.ps)  in si_parse_power_table()
6865 			kfree(rdev->pm.dpm.ps);  in si_parse_power_table()
6868 		rdev->pm.dpm.ps[i].ps_priv = ps;  in si_parse_power_table()
6869 		si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in si_parse_power_table()
6884 						  &rdev->pm.dpm.ps[i], k,  in si_parse_power_table()
6890 	rdev->pm.dpm.num_ps = state_array->ucNumEntries;  in si_parse_power_table()
6895 		clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;  in si_parse_power_table()
6902 		rdev->pm.dpm.vce_states[i].sclk = sclk;  in si_parse_power_table()
6903 		rdev->pm.dpm.vce_states[i].mclk = mclk;  in si_parse_power_table()
6922 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6958 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in si_dpm_init()
6960 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in si_dpm_init()
6964 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in si_dpm_init()
6965 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in si_dpm_init()
6966 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in si_dpm_init()
6967 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in si_dpm_init()
6968 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in si_dpm_init()
6969 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in si_dpm_init()
6970 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in si_dpm_init()
6971 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in si_dpm_init()
6972 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in si_dpm_init()
6974 	if (rdev->pm.dpm.voltage_response_time == 0)  in si_dpm_init()
6975 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in si_dpm_init()
6976 	if (rdev->pm.dpm.backbias_response_time == 0)  in si_dpm_init()
6977 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in si_dpm_init()
7054 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;  in si_dpm_init()
7055 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;  in si_dpm_init()
7056 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in si_dpm_init()
7057 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;  in si_dpm_init()
7058 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;  in si_dpm_init()
7059 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in si_dpm_init()
7060 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in si_dpm_init()
7065 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in si_dpm_init()
7066 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in si_dpm_init()
7067 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in si_dpm_init()
7068 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_dpm_init()
7079 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in si_dpm_fini()
7080 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in si_dpm_fini()
7082 	kfree(rdev->pm.dpm.ps);  in si_dpm_fini()
7083 	kfree(rdev->pm.dpm.priv);  in si_dpm_fini()
7084 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in si_dpm_fini()