Lines Matching refs:tmp
1311 u32 tmp; in si_get_xclk() local
1313 tmp = RREG32(CG_CLKPIN_CNTL_2); in si_get_xclk()
1314 if (tmp & MUX_TCLK_TO_XCLK) in si_get_xclk()
1317 tmp = RREG32(CG_CLKPIN_CNTL); in si_get_xclk()
1318 if (tmp & XTALIN_DIVIDE) in si_get_xclk()
1916 u32 tmp, buffer_alloc, i; in dce6_line_buffer_adjust() local
1933 tmp = 0; /* 1/2 */ in dce6_line_buffer_adjust()
1936 tmp = 2; /* whole */ in dce6_line_buffer_adjust()
1940 tmp = 0; in dce6_line_buffer_adjust()
1945 DC_LB_MEMORY_CONFIG(tmp)); in dce6_line_buffer_adjust()
1957 switch (tmp) { in dce6_line_buffer_adjust()
1972 u32 tmp = RREG32(MC_SHARED_CHMAP); in si_get_number_of_dram_channels() local
1974 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in si_get_number_of_dram_channels()
2156 u32 tmp, dmif_size = 12288; in dce6_latency_watermark() local
2183 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); in dce6_latency_watermark()
2191 lb_fill_bw = min(tmp, dfixed_trunc(b)); in dce6_latency_watermark()
2264 u32 tmp, arb_control3; in dce6_program_watermarks() local
2386 tmp = arb_control3; in dce6_program_watermarks()
2387 tmp &= ~LATENCY_WATERMARK_MASK(3); in dce6_program_watermarks()
2388 tmp |= LATENCY_WATERMARK_MASK(1); in dce6_program_watermarks()
2389 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2394 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2395 tmp &= ~LATENCY_WATERMARK_MASK(3); in dce6_program_watermarks()
2396 tmp |= LATENCY_WATERMARK_MASK(2); in dce6_program_watermarks()
2397 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
3096 u32 tmp; in si_gpu_init() local
3210 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; in si_gpu_init()
3211 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in si_gpu_init()
3344 tmp = RREG32(HDP_MISC_CNTL); in si_gpu_init()
3345 tmp |= HDP_FLUSH_INVALIDATE_CACHE; in si_gpu_init()
3346 WREG32(HDP_MISC_CNTL, tmp); in si_gpu_init()
3648 u32 tmp; in si_cp_resume() local
3667 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3669 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3671 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3674 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3685 tmp |= RB_NO_UPDATE; in si_cp_resume()
3690 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3698 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3700 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3702 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3705 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3714 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3722 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3724 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3726 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3729 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3738 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3774 u32 tmp; in si_gpu_check_soft_reset() local
3777 tmp = RREG32(GRBM_STATUS); in si_gpu_check_soft_reset()
3778 if (tmp & (PA_BUSY | SC_BUSY | in si_gpu_check_soft_reset()
3786 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | in si_gpu_check_soft_reset()
3790 if (tmp & GRBM_EE_BUSY) in si_gpu_check_soft_reset()
3794 tmp = RREG32(GRBM_STATUS2); in si_gpu_check_soft_reset()
3795 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) in si_gpu_check_soft_reset()
3799 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3800 if (!(tmp & DMA_IDLE)) in si_gpu_check_soft_reset()
3804 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3805 if (!(tmp & DMA_IDLE)) in si_gpu_check_soft_reset()
3809 tmp = RREG32(SRBM_STATUS2); in si_gpu_check_soft_reset()
3810 if (tmp & DMA_BUSY) in si_gpu_check_soft_reset()
3813 if (tmp & DMA1_BUSY) in si_gpu_check_soft_reset()
3817 tmp = RREG32(SRBM_STATUS); in si_gpu_check_soft_reset()
3819 if (tmp & IH_BUSY) in si_gpu_check_soft_reset()
3822 if (tmp & SEM_BUSY) in si_gpu_check_soft_reset()
3825 if (tmp & GRBM_RQ_PENDING) in si_gpu_check_soft_reset()
3828 if (tmp & VMC_BUSY) in si_gpu_check_soft_reset()
3831 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | in si_gpu_check_soft_reset()
3839 tmp = RREG32(VM_L2_STATUS); in si_gpu_check_soft_reset()
3840 if (tmp & L2_BUSY) in si_gpu_check_soft_reset()
3856 u32 tmp; in si_gpu_soft_reset() local
3881 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3882 tmp &= ~DMA_RB_ENABLE; in si_gpu_soft_reset()
3883 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3887 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3888 tmp &= ~DMA_RB_ENABLE; in si_gpu_soft_reset()
3889 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3948 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3949 tmp |= grbm_soft_reset; in si_gpu_soft_reset()
3950 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3951 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3952 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3956 tmp &= ~grbm_soft_reset; in si_gpu_soft_reset()
3957 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3958 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3962 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3963 tmp |= srbm_soft_reset; in si_gpu_soft_reset()
3964 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3965 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3966 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3970 tmp &= ~srbm_soft_reset; in si_gpu_soft_reset()
3971 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3972 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3986 u32 tmp, i; in si_set_clk_bypass_mode() local
3988 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3989 tmp |= SPLL_BYPASS_EN; in si_set_clk_bypass_mode()
3990 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
3992 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3993 tmp |= SPLL_CTLREQ_CHG; in si_set_clk_bypass_mode()
3994 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4003 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); in si_set_clk_bypass_mode()
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4006 tmp = RREG32(MPLL_CNTL_MODE); in si_set_clk_bypass_mode()
4007 tmp &= ~MPLL_MCLK_SEL; in si_set_clk_bypass_mode()
4008 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
4013 u32 tmp; in si_spll_powerdown() local
4015 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4016 tmp |= SPLL_SW_DIR_CONTROL; in si_spll_powerdown()
4017 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4019 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4020 tmp |= SPLL_RESET; in si_spll_powerdown()
4021 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4023 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4024 tmp |= SPLL_SLEEP; in si_spll_powerdown()
4025 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4027 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4028 tmp &= ~SPLL_SW_DIR_CONTROL; in si_spll_powerdown()
4029 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4035 u32 tmp, i; in si_gpu_pci_config_reset() local
4048 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4049 tmp &= ~DMA_RB_ENABLE; in si_gpu_pci_config_reset()
4050 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4052 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4053 tmp &= ~DMA_RB_ENABLE; in si_gpu_pci_config_reset()
4054 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4136 u32 tmp; in si_mc_program() local
4163 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in si_mc_program()
4164 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in si_mc_program()
4165 WREG32(MC_VM_FB_LOCATION, tmp); in si_mc_program()
4200 u32 tmp; in si_mc_init() local
4205 tmp = RREG32(MC_ARB_RAMCFG); in si_mc_init()
4206 if (tmp & CHANSIZE_OVERRIDE) { in si_mc_init()
4208 } else if (tmp & CHANSIZE_MASK) { in si_mc_init()
4213 tmp = RREG32(MC_SHARED_CHMAP); in si_mc_init()
4214 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in si_mc_init()
4249 tmp = RREG32(CONFIG_MEMSIZE); in si_mc_init()
4251 if (tmp & 0xffff0000) { in si_mc_init()
4252 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in si_mc_init()
4253 if (tmp & 0xffff) in si_mc_init()
4254 tmp &= 0xffff; in si_mc_init()
4256 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; in si_mc_init()
5135 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt() local
5140 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5142 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5143 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5147 tmp = RREG32(DB_DEPTH_INFO); in si_enable_gui_idle_interrupt()
5161 u32 tmp, tmp2; in si_set_uvd_dcm() local
5163 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm()
5164 tmp &= ~(CLK_OD_MASK | CG_DT_MASK); in si_set_uvd_dcm()
5165 tmp |= DCM | CG_DT(1) | CLK_OD(4); in si_set_uvd_dcm()
5168 tmp &= ~0x7ffff800; in si_set_uvd_dcm()
5171 tmp |= 0x7ffff800; in si_set_uvd_dcm()
5175 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5186 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg() local
5187 tmp &= ~DCM; in si_init_uvd_internal_cg()
5188 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5210 u32 tmp; in si_update_rlc() local
5212 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5213 if (tmp != rlc) in si_update_rlc()
5232 u32 tmp; in si_init_dma_pg() local
5237 for (tmp = 0; tmp < 5; tmp++) in si_init_dma_pg()
5244 u32 tmp; in si_enable_gfx_cgpg() local
5247 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); in si_enable_gfx_cgpg()
5248 WREG32(RLC_TTOP_D, tmp); in si_enable_gfx_cgpg()
5250 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5251 tmp |= GFX_PG_ENABLE; in si_enable_gfx_cgpg()
5252 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5254 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5255 tmp |= AUTO_PG_EN; in si_enable_gfx_cgpg()
5256 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5258 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5259 tmp &= ~AUTO_PG_EN; in si_enable_gfx_cgpg()
5260 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5262 tmp = RREG32(DB_RENDER_CONTROL); in si_enable_gfx_cgpg()
5268 u32 tmp; in si_init_gfx_cgpg() local
5272 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5273 tmp |= GFX_PG_SRC; in si_init_gfx_cgpg()
5274 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
5278 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_init_gfx_cgpg()
5280 tmp &= ~GRBM_REG_SGIT_MASK; in si_init_gfx_cgpg()
5281 tmp |= GRBM_REG_SGIT(0x700); in si_init_gfx_cgpg()
5282 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; in si_init_gfx_cgpg()
5283 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_init_gfx_cgpg()
5288 u32 mask = 0, tmp, tmp1; in si_get_cu_active_bitmap() local
5292 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in si_get_cu_active_bitmap()
5296 tmp &= 0xffff0000; in si_get_cu_active_bitmap()
5298 tmp |= tmp1; in si_get_cu_active_bitmap()
5299 tmp >>= 16; in si_get_cu_active_bitmap()
5306 return (~tmp) & mask; in si_get_cu_active_bitmap()
5313 u32 tmp = 0; in si_init_ao_cu_mask() local
5330 tmp |= (cu_bitmap << (i * 16 + j * 8)); in si_init_ao_cu_mask()
5334 WREG32(RLC_PG_AO_CU_MASK, tmp); in si_init_ao_cu_mask()
5336 tmp = RREG32(RLC_MAX_PG_CU); in si_init_ao_cu_mask()
5337 tmp &= ~MAX_PU_CU_MASK; in si_init_ao_cu_mask()
5338 tmp |= MAX_PU_CU(active_cu_number); in si_init_ao_cu_mask()
5339 WREG32(RLC_MAX_PG_CU, tmp); in si_init_ao_cu_mask()
5345 u32 data, orig, tmp; in si_enable_cgcg() local
5354 tmp = si_halt_rlc(rdev); in si_enable_cgcg()
5362 si_update_rlc(rdev, tmp); in si_enable_cgcg()
5385 u32 data, orig, tmp = 0; in si_enable_mgcg() local
5405 tmp = si_halt_rlc(rdev); in si_enable_mgcg()
5411 si_update_rlc(rdev, tmp); in si_enable_mgcg()
5428 tmp = si_halt_rlc(rdev); in si_enable_mgcg()
5434 si_update_rlc(rdev, tmp); in si_enable_mgcg()
5441 u32 orig, data, tmp; in si_enable_uvd_mgcg() local
5444 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5445 tmp |= 0x3fff; in si_enable_uvd_mgcg()
5446 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
5456 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5457 tmp &= ~0x3fff; in si_enable_uvd_mgcg()
5458 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
5796 u32 tmp = RREG32(GRBM_SOFT_RESET); in si_rlc_reset() local
5798 tmp |= SOFT_RESET_RLC; in si_rlc_reset()
5799 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5801 tmp &= ~SOFT_RESET_RLC; in si_rlc_reset()
5802 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5826 u32 tmp; in si_lbpw_supported() local
5829 tmp = RREG32(MC_SEQ_MISC0); in si_lbpw_supported()
5830 if ((tmp & 0xF0000000) == 0xB0000000) in si_lbpw_supported()
5837 u32 tmp; in si_enable_lbpw() local
5839 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5841 tmp |= LOAD_BALANCE_ENABLE; in si_enable_lbpw()
5843 tmp &= ~LOAD_BALANCE_ENABLE; in si_enable_lbpw()
5844 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5937 u32 tmp; in si_disable_interrupt_state() local
5939 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5941 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5945 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5947 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5979 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5980 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state()
5981 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5982 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_disable_interrupt_state()
5983 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5984 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_disable_interrupt_state()
5985 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5986 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_disable_interrupt_state()
5987 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5988 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_disable_interrupt_state()
5989 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5990 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_disable_interrupt_state()
6247 u32 tmp; in si_irq_ack() local
6313 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6314 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6315 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6318 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6319 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6320 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6323 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6324 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6325 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6328 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6329 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6330 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6333 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6334 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6335 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6338 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6339 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6340 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6344 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6345 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6346 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6349 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6350 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6351 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6354 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6355 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6356 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6359 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6360 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6361 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6364 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6365 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6366 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6369 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6370 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6371 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6398 u32 wptr, tmp; in si_get_ih_wptr() local
6414 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6415 tmp |= IH_WPTR_OVERFLOW_CLEAR; in si_get_ih_wptr()
6416 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
7468 u32 max_lw, current_lw, tmp; in si_pcie_gen3_enable() local
7479 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7480 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; in si_pcie_gen3_enable()
7481 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; in si_pcie_gen3_enable()
7484 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_pcie_gen3_enable()
7485 if (tmp & LC_RENEGOTIATION_SUPPORT) { in si_pcie_gen3_enable()
7486 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); in si_pcie_gen3_enable()
7487 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); in si_pcie_gen3_enable()
7488 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; in si_pcie_gen3_enable()
7489 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); in si_pcie_gen3_enable()
7505 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7506 tmp |= LC_SET_QUIESCE; in si_pcie_gen3_enable()
7507 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()
7509 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7510 tmp |= LC_REDO_EQ; in si_pcie_gen3_enable()
7511 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()
7537 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7538 tmp &= ~LC_SET_QUIESCE; in si_pcie_gen3_enable()
7539 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()