Lines Matching refs:rlc
5208 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5213 if (tmp != rlc) in si_update_rlc()
5214 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5270 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5276 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5676 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5684 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5708 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5720 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5772 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5773 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5778 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5779 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
6903 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6904 rdev->rlc.reg_list_size = in si_startup()
6907 rdev->rlc.cs_data = si_cs_data; in si_startup()