4445 				  u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_ce_check()  argument
4447 	switch (pkt->opcode) {  in si_vm_packet3_ce_check()
4460 		DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_ce_check()
4518 				   u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_gfx_check()  argument
4521 	u32 idx = pkt->idx + 1;  in si_vm_packet3_gfx_check()
4525 	switch (pkt->opcode) {  in si_vm_packet3_gfx_check()
4586 				for (i = 0; i < (pkt->count - 2); i++) {  in si_vm_packet3_gfx_check()
4610 		end_reg = 4 * pkt->count + start_reg - 4;  in si_vm_packet3_gfx_check()
4617 		for (i = 0; i < pkt->count; i++) {  in si_vm_packet3_gfx_check()
4629 		DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_gfx_check()
4636 				       u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_compute_check()  argument
4639 	u32 idx = pkt->idx + 1;  in si_vm_packet3_compute_check()
4643 	switch (pkt->opcode) {  in si_vm_packet3_compute_check()
4689 				for (i = 0; i < (pkt->count - 2); i++) {  in si_vm_packet3_compute_check()
4717 		DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_compute_check()
4727 	struct radeon_cs_packet pkt;  in si_ib_parse()  local
4730 		pkt.idx = idx;  in si_ib_parse()
4731 		pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);  in si_ib_parse()
4732 		pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);  in si_ib_parse()
4733 		pkt.one_reg_wr = 0;  in si_ib_parse()
4734 		switch (pkt.type) {  in si_ib_parse()
4743 			pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);  in si_ib_parse()
4745 				ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4749 					ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4753 					ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4761 			idx += pkt.count + 2;  in si_ib_parse()
4764 			dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);  in si_ib_parse()