3401 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)  in si_ring_ib_execute()  argument
3403 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in si_ring_ib_execute()
3404 	unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;  in si_ring_ib_execute()
3407 	if (ib->is_const_ib) {  in si_ring_ib_execute()
3438 			  (ib->gpu_addr & 0xFFFFFFFC));  in si_ring_ib_execute()
3439 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in si_ring_ib_execute()
3440 	radeon_ring_write(ring, ib->length_dw | (vm_id << 24));  in si_ring_ib_execute()
3442 	if (!ib->is_const_ib) {  in si_ring_ib_execute()
4445 				  u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_ce_check()  argument
4466 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)  in si_vm_packet3_cp_dma_check()  argument
4469 	u32 command = ib[idx + 4];  in si_vm_packet3_cp_dma_check()
4470 	u32 info = ib[idx + 1];  in si_vm_packet3_cp_dma_check()
4471 	u32 idx_value = ib[idx];  in si_vm_packet3_cp_dma_check()
4496 			start_reg = ib[idx + 2];  in si_vm_packet3_cp_dma_check()
4518 				   u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_gfx_check()  argument
4522 	u32 idx_value = ib[idx];  in si_vm_packet3_gfx_check()
4574 			reg = ib[idx + 3] * 4;  in si_vm_packet3_gfx_check()
4581 			start_reg = ib[idx + 1] * 4;  in si_vm_packet3_gfx_check()
4596 			reg = ib[idx + 5] * 4;  in si_vm_packet3_gfx_check()
4603 			reg = ib[idx + 3] * 4;  in si_vm_packet3_gfx_check()
4624 		r = si_vm_packet3_cp_dma_check(ib, idx);  in si_vm_packet3_gfx_check()
4636 				       u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_compute_check()  argument
4640 	u32 idx_value = ib[idx];  in si_vm_packet3_compute_check()
4677 			reg = ib[idx + 3] * 4;  in si_vm_packet3_compute_check()
4684 			start_reg = ib[idx + 1] * 4;  in si_vm_packet3_compute_check()
4699 			reg = ib[idx + 5] * 4;  in si_vm_packet3_compute_check()
4706 			reg = ib[idx + 3] * 4;  in si_vm_packet3_compute_check()
4712 		r = si_vm_packet3_cp_dma_check(ib, idx);  in si_vm_packet3_compute_check()
4723 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)  in si_ib_parse()  argument
4731 		pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);  in si_ib_parse()
4732 		pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);  in si_ib_parse()
4743 			pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);  in si_ib_parse()
4744 			if (ib->is_const_ib)  in si_ib_parse()
4745 				ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4747 				switch (ib->ring) {  in si_ib_parse()
4749 					ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4753 					ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4756 					dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);  in si_ib_parse()
4769 			for (i = 0; i < ib->length_dw; i++) {  in si_ib_parse()
4771 					printk("\t0x%08x <---\n", ib->ptr[i]);  in si_ib_parse()
4773 					printk("\t0x%08x\n", ib->ptr[i]);  in si_ib_parse()
4777 	} while (idx < ib->length_dw);  in si_ib_parse()