3375 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in si_fence_ring_emit()
3438 			  (ib->gpu_addr & 0xFFFFFFFC));  in si_ring_ib_execute()
3439 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in si_ring_ib_execute()
3661 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in si_cp_resume()
3679 	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);  in si_cp_resume()
3680 	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in si_cp_resume()
3692 	WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);  in si_cp_resume()
3710 	WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);  in si_cp_resume()
3711 	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);  in si_cp_resume()
3716 	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);  in si_cp_resume()
3734 	WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);  in si_cp_resume()
3735 	WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);  in si_cp_resume()
3740 	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);  in si_cp_resume()
4162 	       rdev->vram_scratch.gpu_addr >> 12);  in si_mc_program()
6017 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in si_irq_init()
6027 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in si_irq_init()
6038 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);  in si_irq_init()
6039 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in si_irq_init()