Lines Matching refs:gb_addr_config
3092 u32 gb_addr_config = 0; in si_gpu_init() local
3115 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3132 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3150 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3167 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3184 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3220 gb_addr_config &= ~ROW_SIZE_MASK; in si_gpu_init()
3224 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3227 gb_addr_config |= ROW_SIZE(1); in si_gpu_init()
3230 gb_addr_config |= ROW_SIZE(2); in si_gpu_init()
3271 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in si_gpu_init()
3273 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; in si_gpu_init()
3275 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3276 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3277 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
3278 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3279 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3280 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3282 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3283 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3284 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in si_gpu_init()