7781         WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7786         WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7797         WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7813 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
7818 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,  in si_set_vce_clocks()
7823 		WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
7835 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_vce_clocks()
7838 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,  in si_set_vce_clocks()
7842 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
7844 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);  in si_set_vce_clocks()
7847 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7856 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7859 	WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_vce_clocks()
7862 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);  in si_set_vce_clocks()
7865 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);  in si_set_vce_clocks()
7868 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
7876 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7881 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);  in si_set_vce_clocks()
7888 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()