Lines Matching refs:WREG32
1598 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in si_mc_load_microcode()
1602 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1603 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1608 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1609 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1611 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in si_mc_load_microcode()
1612 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in si_mc_load_microcode()
1618 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in si_mc_load_microcode()
1620 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in si_mc_load_microcode()
1624 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1625 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
1626 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in si_mc_load_microcode()
1641 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in si_mc_load_microcode()
1944 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
1947 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
2389 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2390 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2397 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2398 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2402 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2405 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2406 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2700 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
2942 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
2961 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh()
3011 WREG32(SPI_STATIC_THREAD_MGMT_3, data); in si_setup_spi()
3085 WREG32(PA_SC_RASTER_CONFIG, data); in si_setup_rb()
3190 WREG32((0x2c14 + j), 0x00000000); in si_gpu_init()
3191 WREG32((0x2c18 + j), 0x00000000); in si_gpu_init()
3192 WREG32((0x2c1c + j), 0x00000000); in si_gpu_init()
3193 WREG32((0x2c20 + j), 0x00000000); in si_gpu_init()
3194 WREG32((0x2c24 + j), 0x00000000); in si_gpu_init()
3197 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in si_gpu_init()
3198 WREG32(SRBM_INT_CNTL, 1); in si_gpu_init()
3199 WREG32(SRBM_INT_ACK, 1); in si_gpu_init()
3203 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in si_gpu_init()
3275 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3276 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3277 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
3278 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3279 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3280 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3282 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3283 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3284 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3306 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in si_gpu_init()
3308 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in si_gpu_init()
3311 WREG32(SX_DEBUG_1, sx_debug_1); in si_gpu_init()
3313 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in si_gpu_init()
3315 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3320 WREG32(VGT_NUM_INSTANCES, 1); in si_gpu_init()
3322 WREG32(CP_PERFMON_CNTL, 0); in si_gpu_init()
3324 WREG32(SQ_CONFIG, 0); in si_gpu_init()
3326 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in si_gpu_init()
3329 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in si_gpu_init()
3332 WREG32(VGT_GS_VERTEX_REUSE, 16); in si_gpu_init()
3333 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in si_gpu_init()
3335 WREG32(CB_PERFCOUNTER0_SELECT0, 0); in si_gpu_init()
3336 WREG32(CB_PERFCOUNTER0_SELECT1, 0); in si_gpu_init()
3337 WREG32(CB_PERFCOUNTER1_SELECT0, 0); in si_gpu_init()
3338 WREG32(CB_PERFCOUNTER1_SELECT1, 0); in si_gpu_init()
3339 WREG32(CB_PERFCOUNTER2_SELECT0, 0); in si_gpu_init()
3340 WREG32(CB_PERFCOUNTER2_SELECT1, 0); in si_gpu_init()
3341 WREG32(CB_PERFCOUNTER3_SELECT0, 0); in si_gpu_init()
3342 WREG32(CB_PERFCOUNTER3_SELECT1, 0); in si_gpu_init()
3346 WREG32(HDP_MISC_CNTL, tmp); in si_gpu_init()
3349 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in si_gpu_init()
3351 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in si_gpu_init()
3464 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3468 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3469 WREG32(SCRATCH_UMSK, 0); in si_cp_enable()
3504 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3506 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3507 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3513 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3515 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3516 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3522 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3524 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3525 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3531 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3533 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3534 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3538 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3540 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3541 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3545 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3547 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3548 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3551 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3552 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3553 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3554 WREG32(CP_ME_RAM_RADDR, 0); in si_cp_load_microcode()
3654 WREG32(CP_SEM_WAIT_TIMER, 0x0); in si_cp_resume()
3655 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in si_cp_resume()
3658 WREG32(CP_RB_WPTR_DELAY, 0); in si_cp_resume()
3660 WREG32(CP_DEBUG, 0); in si_cp_resume()
3661 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3671 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3674 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3676 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3679 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3680 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3683 WREG32(SCRATCH_UMSK, 0xff); in si_cp_resume()
3686 WREG32(SCRATCH_UMSK, 0); in si_cp_resume()
3690 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3692 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3702 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3705 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3707 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3710 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3711 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3714 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3716 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3726 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3729 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3731 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3734 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3735 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3738 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3740 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3877 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
3883 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3889 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3951 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3957 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3965 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3971 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3990 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
3994 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4008 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
4017 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4021 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4025 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4029 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4046 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
4050 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4054 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4141 WREG32((0x2c14 + j), 0x00000000); in si_mc_program()
4142 WREG32((0x2c18 + j), 0x00000000); in si_mc_program()
4143 WREG32((0x2c1c + j), 0x00000000); in si_mc_program()
4144 WREG32((0x2c20 + j), 0x00000000); in si_mc_program()
4145 WREG32((0x2c24 + j), 0x00000000); in si_mc_program()
4147 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in si_mc_program()
4155 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in si_mc_program()
4157 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in si_mc_program()
4159 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in si_mc_program()
4161 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in si_mc_program()
4165 WREG32(MC_VM_FB_LOCATION, tmp); in si_mc_program()
4167 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
4168 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in si_mc_program()
4169 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in si_mc_program()
4170 WREG32(MC_VM_AGP_BASE, 0); in si_mc_program()
4171 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in si_mc_program()
4172 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in si_mc_program()
4271 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in si_pcie_gart_tlb_flush()
4274 WREG32(VM_INVALIDATE_REQUEST, 1); in si_pcie_gart_tlb_flush()
4289 WREG32(MC_VM_MX_L1_TLB_CNTL, in si_pcie_gart_enable()
4297 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
4303 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4304 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4308 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in si_pcie_gart_enable()
4309 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in si_pcie_gart_enable()
4310 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4311 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4313 WREG32(VM_CONTEXT0_CNTL2, 0); in si_pcie_gart_enable()
4314 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4317 WREG32(0x15D4, 0); in si_pcie_gart_enable()
4318 WREG32(0x15D8, 0); in si_pcie_gart_enable()
4319 WREG32(0x15DC, 0); in si_pcie_gart_enable()
4323 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in si_pcie_gart_enable()
4324 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4331 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in si_pcie_gart_enable()
4334 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in si_pcie_gart_enable()
4339 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4341 WREG32(VM_CONTEXT1_CNTL2, 4); in si_pcie_gart_enable()
4342 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4379 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
4380 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
4382 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in si_pcie_gart_disable()
4385 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
4389 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
4390 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
5143 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5175 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5188 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5200 WREG32(RLC_CNTL, data); in si_halt_rlc()
5214 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5227 WREG32(DMA_PG, data); in si_enable_dma_pg()
5234 WREG32(DMA_PGFSM_WRITE, 0x00002000); in si_init_dma_pg()
5235 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); in si_init_dma_pg()
5238 WREG32(DMA_PGFSM_WRITE, 0); in si_init_dma_pg()
5248 WREG32(RLC_TTOP_D, tmp); in si_enable_gfx_cgpg()
5252 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5256 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5260 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5270 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5274 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
5276 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5283 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_init_gfx_cgpg()
5334 WREG32(RLC_PG_AO_CU_MASK, tmp); in si_init_ao_cu_mask()
5339 WREG32(RLC_MAX_PG_CU, tmp); in si_init_ao_cu_mask()
5352 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); in si_enable_cgcg()
5356 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_cgcg()
5357 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_cgcg()
5358 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); in si_enable_cgcg()
5364 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); in si_enable_cgcg()
5379 WREG32(RLC_CGCG_CGLS_CTRL, data); in si_enable_cgcg()
5391 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5397 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5403 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5407 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5408 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5409 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); in si_enable_mgcg()
5416 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5421 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5426 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5430 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5431 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5432 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); in si_enable_mgcg()
5451 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5463 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5496 WREG32(mc_cg_registers[i], data); in si_enable_mc_ls()
5513 WREG32(mc_cg_registers[i], data); in si_enable_mc_mgcg()
5532 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5533 WREG32(DMA_CLK_CTRL + offset, 0x00000100); in si_enable_dma_mgcg()
5544 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5549 WREG32(DMA_CLK_CTRL + offset, data); in si_enable_dma_mgcg()
5585 WREG32(HDP_HOST_PATH_CNTL, data); in si_enable_hdp_mgcg()
5601 WREG32(HDP_MEM_POWER_LS, data); in si_enable_hdp_ls()
5772 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5773 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5778 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5779 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5799 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5802 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5808 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5817 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
5844 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5848 WREG32(SPI_LB_CU_MASK, 0x00ff); in si_enable_lbpw()
5867 WREG32(RLC_RL_BASE, 0); in si_rlc_resume()
5868 WREG32(RLC_RL_SIZE, 0); in si_rlc_resume()
5869 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
5870 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); in si_rlc_resume()
5871 WREG32(RLC_LB_CNTR_INIT, 0); in si_rlc_resume()
5872 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in si_rlc_resume()
5874 WREG32(RLC_MC_CNTL, 0); in si_rlc_resume()
5875 WREG32(RLC_UCODE_CNTL, 0); in si_rlc_resume()
5887 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5888 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); in si_rlc_resume()
5894 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5895 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in si_rlc_resume()
5898 WREG32(RLC_UCODE_ADDR, 0); in si_rlc_resume()
5914 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5915 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5926 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
5927 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5929 WREG32(IH_RB_RPTR, 0); in si_disable_interrupts()
5930 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
5941 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
5942 WREG32(CP_INT_CNTL_RING1, 0); in si_disable_interrupt_state()
5943 WREG32(CP_INT_CNTL_RING2, 0); in si_disable_interrupt_state()
5945 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5947 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5948 WREG32(GRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5949 WREG32(SRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5951 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5952 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5955 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5956 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5959 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5960 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5964 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5965 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5968 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5969 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5972 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5973 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5977 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in si_disable_interrupt_state()
5980 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state()
5982 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_disable_interrupt_state()
5984 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_disable_interrupt_state()
5986 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_disable_interrupt_state()
5988 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_disable_interrupt_state()
5990 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_disable_interrupt_state()
6017 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in si_irq_init()
6025 WREG32(INTERRUPT_CNTL, interrupt_cntl); in si_irq_init()
6027 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
6038 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in si_irq_init()
6039 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
6041 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6044 WREG32(IH_RB_RPTR, 0); in si_irq_init()
6045 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6052 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
6182 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
6183 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); in si_irq_set()
6184 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); in si_irq_set()
6186 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6187 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
6189 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in si_irq_set()
6197 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
6198 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
6201 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
6202 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in si_irq_set()
6205 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in si_irq_set()
6206 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()
6210 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in si_irq_set()
6212 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in si_irq_set()
6216 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in si_irq_set()
6218 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in si_irq_set()
6222 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in si_irq_set()
6224 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in si_irq_set()
6229 WREG32(DC_HPD1_INT_CONTROL, hpd1); in si_irq_set()
6230 WREG32(DC_HPD2_INT_CONTROL, hpd2); in si_irq_set()
6231 WREG32(DC_HPD3_INT_CONTROL, hpd3); in si_irq_set()
6232 WREG32(DC_HPD4_INT_CONTROL, hpd4); in si_irq_set()
6233 WREG32(DC_HPD5_INT_CONTROL, hpd5); in si_irq_set()
6234 WREG32(DC_HPD6_INT_CONTROL, hpd6); in si_irq_set()
6237 WREG32(CG_THERMAL_INT, thermal_int); in si_irq_set()
6270 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6272 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6274 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6276 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6278 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6280 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6284 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6286 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6288 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6290 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6292 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6294 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6299 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6301 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6303 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6305 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6307 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6309 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6315 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6320 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6325 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6330 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6335 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6340 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6346 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6351 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6356 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6361 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6366 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6371 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6416 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
6776 WREG32(SRBM_INT_ACK, 0x1); in si_irq_process()
6849 WREG32(IH_RB_RPTR, rptr); in si_irq_process()
7315 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in si_get_gpu_clock_counter()
7722 WREG32(THM_CLK_CNTL, data); in si_program_aspm()
7728 WREG32(MISC_CLK_CNTL, data); in si_program_aspm()
7733 WREG32(CG_CLKPIN_CNTL, data); in si_program_aspm()
7738 WREG32(CG_CLKPIN_CNTL_2, data); in si_program_aspm()
7744 WREG32(MPLL_BYPASSCLK_SEL, data); in si_program_aspm()
7749 WREG32(SPLL_CNTL_MODE, data); in si_program_aspm()