2471 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2481 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2491 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2501 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2511 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2521 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2531 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2541 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2551 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2561 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2571 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2581 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2591 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2601 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2611 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2621 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2631 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2641 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2651 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2661 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2671 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2681 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2691 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2713 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2723 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2733 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2743 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2753 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2763 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2773 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2783 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2793 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2803 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2813 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2823 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2833 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2843 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2853 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2863 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2873 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2883 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2893 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2903 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2913 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2923 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2933 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()