1311 	u32 tmp;  in si_get_xclk()  local
1916 	u32 tmp, buffer_alloc, i;  in dce6_line_buffer_adjust()  local
1972 	u32 tmp = RREG32(MC_SHARED_CHMAP);  in si_get_number_of_dram_channels()  local
2156 	u32 tmp, dmif_size = 12288;  in dce6_latency_watermark()  local
2264 	u32 tmp, arb_control3;  in dce6_program_watermarks()  local
3096 	u32 tmp;  in si_gpu_init()  local
3648 	u32 tmp;  in si_cp_resume()  local
3774 	u32 tmp;  in si_gpu_check_soft_reset()  local
3856 	u32 tmp;  in si_gpu_soft_reset()  local
3986 	u32 tmp, i;  in si_set_clk_bypass_mode()  local
4013 	u32 tmp;  in si_spll_powerdown()  local
4035 	u32 tmp, i;  in si_gpu_pci_config_reset()  local
4136 	u32 tmp;  in si_mc_program()  local
4200 	u32 tmp;  in si_mc_init()  local
5135 	u32 tmp = RREG32(CP_INT_CNTL_RING0);  in si_enable_gui_idle_interrupt()  local
5161 	u32 tmp, tmp2;  in si_set_uvd_dcm()  local
5186 		u32 tmp = RREG32(UVD_CGC_CTRL);  in si_init_uvd_internal_cg()  local
5210 	u32 tmp;  in si_update_rlc()  local
5232 	u32 tmp;  in si_init_dma_pg()  local
5244 	u32 tmp;  in si_enable_gfx_cgpg()  local
5268 	u32 tmp;  in si_init_gfx_cgpg()  local
5288 	u32 mask = 0, tmp, tmp1;  in si_get_cu_active_bitmap()  local
5313 	u32 tmp = 0;  in si_init_ao_cu_mask()  local
5345 	u32 data, orig, tmp;  in si_enable_cgcg()  local
5385 	u32 data, orig, tmp = 0;  in si_enable_mgcg()  local
5441 	u32 orig, data, tmp;  in si_enable_uvd_mgcg()  local
5796 	u32 tmp = RREG32(GRBM_SOFT_RESET);  in si_rlc_reset()  local
5826 	u32 tmp;  in si_lbpw_supported()  local
5837 	u32 tmp;  in si_enable_lbpw()  local
5937 	u32 tmp;  in si_disable_interrupt_state()  local
6247 	u32 tmp;  in si_irq_ack()  local
6398 	u32 wptr, tmp;  in si_get_ih_wptr()  local
7468 			u32 max_lw, current_lw, tmp;  in si_pcie_gen3_enable()  local