Lines Matching refs:u32

29 	u32 cg_spll_func_cntl;
30 	u32 cg_spll_func_cntl_2;
31 	u32 cg_spll_func_cntl_3;
32 	u32 cg_spll_spread_spectrum;
33 	u32 cg_spll_spread_spectrum_2;
34 	u32 mpll_ad_func_cntl;
35 	u32 mpll_ad_func_cntl_2;
36 	u32 mpll_dq_func_cntl;
37 	u32 mpll_dq_func_cntl_2;
38 	u32 mclk_pwrmgt_cntl;
39 	u32 dll_cntl;
40 	u32 mpll_ss1;
41 	u32 mpll_ss2;
45 	u32 cg_spll_func_cntl;
46 	u32 cg_spll_func_cntl_2;
47 	u32 cg_spll_func_cntl_3;
48 	u32 cg_spll_spread_spectrum;
49 	u32 cg_spll_spread_spectrum_2;
50 	u32 mclk_pwrmgt_cntl;
51 	u32 dll_cntl;
52 	u32 mpll_func_cntl;
53 	u32 mpll_func_cntl2;
54 	u32 mpll_func_cntl3;
55 	u32 mpll_ss;
56 	u32 mpll_ss2;
68 	u32 low_smio;
96 	u32 s0_vid_lower_smio_cntl;
98 	u32 vddc_mask_low;
99 	u32 mvdd_mask_low;
100 	u32 mvdd_split_frequency;
101 	u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
108 	u32 mclk_odt_threshold;
112 	u32 boot_sclk;
114 	u32 ref_div;
115 	u32 active_auto_throttle_sources;
116 	u32 mclk_stutter_mode_threshold;
117 	u32 mclk_strobe_mode_threshold;
118 	u32 mclk_edc_enable_threshold;
119 	u32 bsp;
120 	u32 bsu;
121 	u32 pbsp;
122 	u32 pbsu;
123 	u32 dsp;
124 	u32 psp;
125 	u32 asi;
126 	u32 pasi;
127 	u32 vrc;
128 	u32 restricted_levels;
129 	u32 rlp;
130 	u32 rmp;
131 	u32 lhp;
132 	u32 lmp;
142 	u32 sclk;
143 	u32 mclk;
146 	u32 flags;
180 			      u32 engine_clock,
183 			      u32 engine_clock, u32 memory_clock,
201 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
204 			      u32 engine_clock, u32 memory_clock,
211 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
212 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
213 u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
216 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
219 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
225 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
226 					u32 engine_clock);
282 				  u16 reg_offset, u32 value);