Lines Matching refs:link_width_cntl
1975 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1998 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1999 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2000 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2001 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2002 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2003 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2004 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2006 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2008 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2010 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2011 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2044 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2047 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2049 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2050 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()