Lines Matching refs:rdev
34 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
44 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev) in rv6xx_get_pi() argument
46 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
51 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev) in rv6xx_force_pcie_gen1() argument
64 for (i = 0; i < rdev->usec_timeout; i++) { in rv6xx_force_pcie_gen1()
75 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev) in rv6xx_enable_pcie_gen2_support() argument
88 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, in rv6xx_enable_bif_dynamic_pcie_gen2() argument
101 static void rv6xx_enable_l0s(struct radeon_device *rdev) in rv6xx_enable_l0s() argument
110 static void rv6xx_enable_l1(struct radeon_device *rdev) in rv6xx_enable_l1() argument
122 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev) in rv6xx_enable_pll_sleep_in_l1() argument
139 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev, in rv6xx_convert_clock_to_stepping() argument
145 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in rv6xx_convert_clock_to_stepping()
160 static void rv6xx_output_stepping(struct radeon_device *rdev, in rv6xx_output_stepping() argument
163 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_output_stepping()
164 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
166 u32 spll_step_count = rv6xx_scale_count_given_unit(rdev, in rv6xx_output_stepping()
171 r600_engine_clock_entry_enable(rdev, step_index, true); in rv6xx_output_stepping()
172 r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false); in rv6xx_output_stepping()
175 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false); in rv6xx_output_stepping()
180 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true); in rv6xx_output_stepping()
181 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len); in rv6xx_output_stepping()
187 r600_engine_clock_entry_set_reference_divider(rdev, step_index, in rv6xx_output_stepping()
189 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider); in rv6xx_output_stepping()
190 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count); in rv6xx_output_stepping()
194 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev, in rv6xx_next_vco_step() argument
210 static bool rv6xx_can_step_post_div(struct radeon_device *rdev, in rv6xx_can_step_post_div() argument
219 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev, in rv6xx_next_post_div_step() argument
225 while (rv6xx_can_step_post_div(rdev, &next, target)) in rv6xx_next_post_div_step()
231 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev, in rv6xx_reached_stepping_target() argument
240 static void rv6xx_generate_steps(struct radeon_device *rdev, in rv6xx_generate_steps() argument
249 rv6xx_convert_clock_to_stepping(rdev, low, &cur); in rv6xx_generate_steps()
250 rv6xx_convert_clock_to_stepping(rdev, high, &target); in rv6xx_generate_steps()
252 rv6xx_output_stepping(rdev, step_index++, &cur); in rv6xx_generate_steps()
262 if (rv6xx_can_step_post_div(rdev, &cur, &target)) in rv6xx_generate_steps()
263 next = rv6xx_next_post_div_step(rdev, &cur, &target); in rv6xx_generate_steps()
265 next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT); in rv6xx_generate_steps()
267 if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) { in rv6xx_generate_steps()
269 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT); in rv6xx_generate_steps()
272 if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco)) in rv6xx_generate_steps()
273 rv6xx_output_stepping(rdev, step_index++, &tiny); in rv6xx_generate_steps()
282 rv6xx_output_stepping(rdev, step_index++, &final_vco); in rv6xx_generate_steps()
285 rv6xx_output_stepping(rdev, step_index++, &target); in rv6xx_generate_steps()
288 rv6xx_output_stepping(rdev, step_index++, &next); in rv6xx_generate_steps()
297 static void rv6xx_generate_single_step(struct radeon_device *rdev, in rv6xx_generate_single_step() argument
302 rv6xx_convert_clock_to_stepping(rdev, clock, &step); in rv6xx_generate_single_step()
303 rv6xx_output_stepping(rdev, index, &step); in rv6xx_generate_single_step()
306 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev, in rv6xx_invalidate_intermediate_steps_range() argument
312 r600_engine_clock_entry_enable(rdev, step_index, false); in rv6xx_invalidate_intermediate_steps_range()
315 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev, in rv6xx_set_engine_spread_spectrum_clk_s() argument
322 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev, in rv6xx_set_engine_spread_spectrum_clk_v() argument
329 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_engine_spread_spectrum() argument
340 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev, in rv6xx_set_memory_spread_spectrum_clk_s() argument
346 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev, in rv6xx_set_memory_spread_spectrum_clk_v() argument
352 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_memory_spread_spectrum() argument
361 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_dynamic_spread_spectrum() argument
370 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_enable_post_divider() argument
380 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_post_divider() argument
387 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_feedback_divider() argument
394 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_reference_divider() argument
401 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt) in rv6xx_vid_response_set_brt() argument
406 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev) in rv6xx_enable_engine_feedback_and_reference_sync() argument
418 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev, in rv6xx_scale_count_given_unit() argument
426 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev, in rv6xx_compute_count_for_delay() argument
429 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
431 return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit); in rv6xx_compute_count_for_delay()
434 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_engine_speed_stepping_parameters() argument
437 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_engine_speed_stepping_parameters()
451 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_memory_clock_stepping_parameters() argument
454 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_memory_clock_stepping_parameters()
481 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_voltage_stepping_parameters() argument
484 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_voltage_stepping_parameters()
549 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev, in rv6xx_program_engine_spread_spectrum() argument
552 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
553 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_engine_spread_spectrum()
558 rv6xx_enable_engine_spread_spectrum(rdev, level, false); in rv6xx_program_engine_spread_spectrum()
561 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
565 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_program_engine_spread_spectrum()
576 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v); in rv6xx_program_engine_spread_spectrum()
577 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s); in rv6xx_program_engine_spread_spectrum()
578 rv6xx_enable_engine_spread_spectrum(rdev, level, true); in rv6xx_program_engine_spread_spectrum()
584 … void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry() argument
586 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
588 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
592 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
598 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev, in rv6xx_program_mclk_stepping_entry() argument
603 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs)) in rv6xx_program_mclk_stepping_entry()
607 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); in rv6xx_program_mclk_stepping_entry()
608 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
609 rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div); in rv6xx_program_mclk_stepping_entry()
612 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true); in rv6xx_program_mclk_stepping_entry()
614 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false); in rv6xx_program_mclk_stepping_entry()
619 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_mclk_stepping_parameters_except_lowest_entry() argument
621 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_stepping_parameters_except_lowest_entry()
626 rv6xx_program_mclk_stepping_entry(rdev, i, in rv6xx_program_mclk_stepping_parameters_except_lowest_entry()
631 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, in rv6xx_find_memory_clock_with_highest_vco() argument
637 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_find_memory_clock_with_highest_vco()
641 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, in rv6xx_find_memory_clock_with_highest_vco()
653 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev) in rv6xx_program_mclk_spread_spectrum_parameters() argument
655 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_spread_spectrum_parameters()
656 u32 ref_clk = rdev->clock.mpll.reference_freq; in rv6xx_program_mclk_spread_spectrum_parameters()
661 rv6xx_enable_memory_spread_spectrum(rdev, false); in rv6xx_program_mclk_spread_spectrum_parameters()
664 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
670 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
676 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
683 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_program_mclk_spread_spectrum_parameters()
694 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v); in rv6xx_program_mclk_spread_spectrum_parameters()
695 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s); in rv6xx_program_mclk_spread_spectrum_parameters()
696 rv6xx_enable_memory_spread_spectrum(rdev, true); in rv6xx_program_mclk_spread_spectrum_parameters()
702 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev, in rv6xx_program_voltage_stepping_entry() argument
708 ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage, in rv6xx_program_voltage_stepping_entry()
714 r600_voltage_control_program_voltages(rdev, entry, set_pins); in rv6xx_program_voltage_stepping_entry()
719 …atic void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_voltage_stepping_parameters_except_lowest_entry() argument
721 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_voltage_stepping_parameters_except_lowest_entry()
725 rv6xx_program_voltage_stepping_entry(rdev, i, in rv6xx_program_voltage_stepping_parameters_except_lowest_entry()
730 …tic void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_backbias_stepping_parameters_except_lowest_entry() argument
732 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
745 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry() argument
747 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry()
749 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry()
754 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_mclk_stepping_parameters_lowest_entry() argument
756 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_stepping_parameters_lowest_entry()
759 rv6xx_program_mclk_stepping_entry(rdev, 0, in rv6xx_program_mclk_stepping_parameters_lowest_entry()
763 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_voltage_stepping_parameters_lowest_entry() argument
765 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_voltage_stepping_parameters_lowest_entry()
767 rv6xx_program_voltage_stepping_entry(rdev, 0, in rv6xx_program_voltage_stepping_parameters_lowest_entry()
772 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_backbias_stepping_parameters_lowest_entry() argument
774 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
782 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev, in calculate_memory_refresh_rate() argument
795 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev) in rv6xx_program_memory_timing_parameters() argument
797 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_memory_timing_parameters()
809 radeon_atom_set_engine_dram_timings(rdev, high_clock, 0); in rv6xx_program_memory_timing_parameters()
818 (POWERMODE0(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
820 POWERMODE1(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
822 POWERMODE2(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
824 POWERMODE3(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
829 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev) in rv6xx_program_mpll_timing_parameters() argument
831 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mpll_timing_parameters()
833 r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT * in rv6xx_program_mpll_timing_parameters()
835 r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT); in rv6xx_program_mpll_timing_parameters()
838 static void rv6xx_program_bsp(struct radeon_device *rdev) in rv6xx_program_bsp() argument
840 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_bsp()
841 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
848 r600_set_bsp(rdev, pi->bsu, pi->bsp); in rv6xx_program_bsp()
851 static void rv6xx_program_at(struct radeon_device *rdev) in rv6xx_program_at() argument
853 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_at()
855 r600_set_at(rdev, in rv6xx_program_at()
862 static void rv6xx_program_git(struct radeon_device *rdev) in rv6xx_program_git() argument
864 r600_set_git(rdev, R600_GICST_DFLT); in rv6xx_program_git()
867 static void rv6xx_program_tp(struct radeon_device *rdev) in rv6xx_program_tp() argument
872 r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]); in rv6xx_program_tp()
874 r600_select_td(rdev, R600_TD_DFLT); in rv6xx_program_tp()
877 static void rv6xx_program_vc(struct radeon_device *rdev) in rv6xx_program_vc() argument
879 r600_set_vrc(rdev, R600_VRC_DFLT); in rv6xx_program_vc()
882 static void rv6xx_clear_vc(struct radeon_device *rdev) in rv6xx_clear_vc() argument
884 r600_set_vrc(rdev, 0); in rv6xx_clear_vc()
887 static void rv6xx_program_tpp(struct radeon_device *rdev) in rv6xx_program_tpp() argument
889 r600_set_tpu(rdev, R600_TPU_DFLT); in rv6xx_program_tpp()
890 r600_set_tpc(rdev, R600_TPC_DFLT); in rv6xx_program_tpp()
893 static void rv6xx_program_sstp(struct radeon_device *rdev) in rv6xx_program_sstp() argument
895 r600_set_sstu(rdev, R600_SSTU_DFLT); in rv6xx_program_sstp()
896 r600_set_sst(rdev, R600_SST_DFLT); in rv6xx_program_sstp()
899 static void rv6xx_program_fcp(struct radeon_device *rdev) in rv6xx_program_fcp() argument
901 r600_set_fctu(rdev, R600_FCTU_DFLT); in rv6xx_program_fcp()
902 r600_set_fct(rdev, R600_FCT_DFLT); in rv6xx_program_fcp()
905 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev) in rv6xx_program_vddc3d_parameters() argument
907 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); in rv6xx_program_vddc3d_parameters()
908 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); in rv6xx_program_vddc3d_parameters()
909 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); in rv6xx_program_vddc3d_parameters()
910 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); in rv6xx_program_vddc3d_parameters()
911 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); in rv6xx_program_vddc3d_parameters()
914 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev) in rv6xx_program_voltage_timing_parameters() argument
918 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); in rv6xx_program_voltage_timing_parameters()
920 r600_vid_rt_set_vrt(rdev, in rv6xx_program_voltage_timing_parameters()
921 rv6xx_compute_count_for_delay(rdev, in rv6xx_program_voltage_timing_parameters()
922 rdev->pm.dpm.voltage_response_time, in rv6xx_program_voltage_timing_parameters()
925 rt = rv6xx_compute_count_for_delay(rdev, in rv6xx_program_voltage_timing_parameters()
926 rdev->pm.dpm.backbias_response_time, in rv6xx_program_voltage_timing_parameters()
929 rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5); in rv6xx_program_voltage_timing_parameters()
932 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev) in rv6xx_program_engine_speed_parameters() argument
934 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); in rv6xx_program_engine_speed_parameters()
935 rv6xx_enable_engine_feedback_and_reference_sync(rdev); in rv6xx_program_engine_speed_parameters()
938 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev) in rv6xx_get_master_voltage_mask() argument
940 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_get_master_voltage_mask()
948 ret = radeon_atom_get_voltage_gpio_settings(rdev, in rv6xx_get_master_voltage_mask()
960 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev) in rv6xx_program_voltage_gpio_pins() argument
962 r600_voltage_control_enable_pins(rdev, in rv6xx_program_voltage_gpio_pins()
963 rv6xx_get_master_voltage_mask(rdev)); in rv6xx_program_voltage_gpio_pins()
966 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev, in rv6xx_enable_static_voltage_control() argument
973 radeon_atom_set_voltage(rdev, in rv6xx_enable_static_voltage_control()
977 r600_voltage_control_deactivate_static_control(rdev, in rv6xx_enable_static_voltage_control()
978 rv6xx_get_master_voltage_mask(rdev)); in rv6xx_enable_static_voltage_control()
981 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable) in rv6xx_enable_display_gap() argument
997 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev) in rv6xx_program_power_level_enter_state() argument
999 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM); in rv6xx_program_power_level_enter_state()
1019 static void rv6xx_calculate_ap(struct radeon_device *rdev, in rv6xx_calculate_ap() argument
1022 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_ap()
1046 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_stepping_parameters() argument
1051 rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1052 rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1053 rv6xx_calculate_voltage_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1054 rv6xx_calculate_ap(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1057 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_stepping_parameters_except_lowest_entry() argument
1059 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1061 rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1063 rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1064 rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1065 rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1066 rv6xx_program_mclk_spread_spectrum_parameters(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1067 rv6xx_program_memory_timing_parameters(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1070 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_stepping_parameters_lowest_entry() argument
1072 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1074 rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1076 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1077 rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1078 rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1081 static void rv6xx_program_power_level_low(struct radeon_device *rdev) in rv6xx_program_power_level_low() argument
1083 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_low()
1085 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1087 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1089 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1091 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1093 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1097 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev) in rv6xx_program_power_level_low_to_lowest_state() argument
1099 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_low_to_lowest_state()
1101 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1102 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1103 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1105 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low_to_lowest_state()
1108 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low_to_lowest_state()
1113 static void rv6xx_program_power_level_medium(struct radeon_device *rdev) in rv6xx_program_power_level_medium() argument
1115 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_medium()
1117 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1119 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1121 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1123 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1125 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1129 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev) in rv6xx_program_power_level_medium_for_transition() argument
1131 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_medium_for_transition()
1133 rv6xx_program_mclk_stepping_entry(rdev, in rv6xx_program_power_level_medium_for_transition()
1137 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1); in rv6xx_program_power_level_medium_for_transition()
1139 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1141 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1144 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1147 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_program_power_level_medium_for_transition()
1149 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1153 static void rv6xx_program_power_level_high(struct radeon_device *rdev) in rv6xx_program_power_level_high() argument
1155 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_high()
1157 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1159 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1161 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1164 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1167 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1171 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable) in rv6xx_enable_backbias() argument
1181 static void rv6xx_program_display_gap(struct radeon_device *rdev) in rv6xx_program_display_gap() argument
1186 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv6xx_program_display_gap()
1189 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv6xx_program_display_gap()
1199 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev, in rv6xx_set_sw_voltage_to_safe() argument
1210 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_set_sw_voltage_to_safe()
1217 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev, in rv6xx_set_sw_voltage_to_low() argument
1222 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_set_sw_voltage_to_low()
1229 static void rv6xx_set_safe_backbias(struct radeon_device *rdev, in rv6xx_set_safe_backbias() argument
1243 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev, in rv6xx_set_safe_pcie_gen2() argument
1252 rv6xx_force_pcie_gen1(rdev); in rv6xx_set_safe_pcie_gen2()
1255 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev, in rv6xx_enable_dynamic_voltage_control() argument
1264 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev, in rv6xx_enable_dynamic_backbias_control() argument
1273 static int rv6xx_step_sw_voltage(struct radeon_device *rdev, in rv6xx_step_sw_voltage() argument
1282 if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1284 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1286 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1297 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_step_sw_voltage()
1299 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_step_sw_voltage()
1305 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev, in rv6xx_step_voltage_if_increasing() argument
1313 return rv6xx_step_sw_voltage(rdev, in rv6xx_step_voltage_if_increasing()
1320 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev, in rv6xx_step_voltage_if_decreasing() argument
1328 return rv6xx_step_sw_voltage(rdev, in rv6xx_step_voltage_if_decreasing()
1335 static void rv6xx_enable_high(struct radeon_device *rdev) in rv6xx_enable_high() argument
1337 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_high()
1341 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); in rv6xx_enable_high()
1344 static void rv6xx_enable_medium(struct radeon_device *rdev) in rv6xx_enable_medium() argument
1346 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_medium()
1349 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_enable_medium()
1352 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in rv6xx_set_dpm_event_sources() argument
1354 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_set_dpm_event_sources()
1389 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev, in rv6xx_enable_auto_throttle_source() argument
1393 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_auto_throttle_source()
1398 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv6xx_enable_auto_throttle_source()
1403 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv6xx_enable_auto_throttle_source()
1409 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev, in rv6xx_enable_thermal_protection() argument
1412 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_thermal_protection()
1415 r600_enable_thermal_protection(rdev, enable); in rv6xx_enable_thermal_protection()
1418 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev, in rv6xx_generate_transition_stepping() argument
1424 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_transition_stepping()
1426 rv6xx_generate_steps(rdev, in rv6xx_generate_transition_stepping()
1432 static void rv6xx_generate_low_step(struct radeon_device *rdev, in rv6xx_generate_low_step() argument
1436 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_low_step()
1439 rv6xx_generate_single_step(rdev, in rv6xx_generate_low_step()
1444 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev) in rv6xx_invalidate_intermediate_steps() argument
1446 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_invalidate_intermediate_steps()
1448 rv6xx_invalidate_intermediate_steps_range(rdev, 0, in rv6xx_invalidate_intermediate_steps()
1452 static void rv6xx_generate_stepping_table(struct radeon_device *rdev, in rv6xx_generate_stepping_table() argument
1456 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_stepping_table()
1460 rv6xx_generate_steps(rdev, in rv6xx_generate_stepping_table()
1465 rv6xx_generate_steps(rdev, in rv6xx_generate_stepping_table()
1472 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_spread_spectrum() argument
1476 rv6xx_enable_dynamic_spread_spectrum(rdev, true); in rv6xx_enable_spread_spectrum()
1478 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_enable_spread_spectrum()
1479 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_enable_spread_spectrum()
1480 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_enable_spread_spectrum()
1481 rv6xx_enable_dynamic_spread_spectrum(rdev, false); in rv6xx_enable_spread_spectrum()
1482 rv6xx_enable_memory_spread_spectrum(rdev, false); in rv6xx_enable_spread_spectrum()
1486 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev) in rv6xx_reset_lvtm_data_sync() argument
1488 if (ASIC_IS_DCE3(rdev)) in rv6xx_reset_lvtm_data_sync()
1494 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev, in rv6xx_enable_dynamic_pcie_gen2() argument
1501 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true); in rv6xx_enable_dynamic_pcie_gen2()
1502 rv6xx_enable_pcie_gen2_support(rdev); in rv6xx_enable_dynamic_pcie_gen2()
1503 r600_enable_dynamic_pcie_gen2(rdev, true); in rv6xx_enable_dynamic_pcie_gen2()
1506 rv6xx_force_pcie_gen1(rdev); in rv6xx_enable_dynamic_pcie_gen2()
1507 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false); in rv6xx_enable_dynamic_pcie_gen2()
1508 r600_enable_dynamic_pcie_gen2(rdev, false); in rv6xx_enable_dynamic_pcie_gen2()
1512 static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, in rv6xx_set_uvd_clock_before_set_eng_clock() argument
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1529 static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, in rv6xx_set_uvd_clock_after_set_eng_clock() argument
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1546 int rv6xx_dpm_enable(struct radeon_device *rdev) in rv6xx_dpm_enable() argument
1548 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_enable()
1549 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_enable()
1551 if (r600_dynamicpm_enabled(rdev)) in rv6xx_dpm_enable()
1554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_enable()
1555 rv6xx_enable_backbias(rdev, true); in rv6xx_dpm_enable()
1558 rv6xx_enable_spread_spectrum(rdev, true); in rv6xx_dpm_enable()
1560 rv6xx_program_mpll_timing_parameters(rdev); in rv6xx_dpm_enable()
1561 rv6xx_program_bsp(rdev); in rv6xx_dpm_enable()
1562 rv6xx_program_git(rdev); in rv6xx_dpm_enable()
1563 rv6xx_program_tp(rdev); in rv6xx_dpm_enable()
1564 rv6xx_program_tpp(rdev); in rv6xx_dpm_enable()
1565 rv6xx_program_sstp(rdev); in rv6xx_dpm_enable()
1566 rv6xx_program_fcp(rdev); in rv6xx_dpm_enable()
1567 rv6xx_program_vddc3d_parameters(rdev); in rv6xx_dpm_enable()
1568 rv6xx_program_voltage_timing_parameters(rdev); in rv6xx_dpm_enable()
1569 rv6xx_program_engine_speed_parameters(rdev); in rv6xx_dpm_enable()
1571 rv6xx_enable_display_gap(rdev, true); in rv6xx_dpm_enable()
1573 rv6xx_enable_display_gap(rdev, false); in rv6xx_dpm_enable()
1575 rv6xx_program_power_level_enter_state(rdev); in rv6xx_dpm_enable()
1577 rv6xx_calculate_stepping_parameters(rdev, boot_ps); in rv6xx_dpm_enable()
1580 rv6xx_program_voltage_gpio_pins(rdev); in rv6xx_dpm_enable()
1582 rv6xx_generate_stepping_table(rdev, boot_ps); in rv6xx_dpm_enable()
1584 rv6xx_program_stepping_parameters_except_lowest_entry(rdev); in rv6xx_dpm_enable()
1585 rv6xx_program_stepping_parameters_lowest_entry(rdev); in rv6xx_dpm_enable()
1587 rv6xx_program_power_level_low(rdev); in rv6xx_dpm_enable()
1588 rv6xx_program_power_level_medium(rdev); in rv6xx_dpm_enable()
1589 rv6xx_program_power_level_high(rdev); in rv6xx_dpm_enable()
1590 rv6xx_program_vc(rdev); in rv6xx_dpm_enable()
1591 rv6xx_program_at(rdev); in rv6xx_dpm_enable()
1593 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_enable()
1594 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_enable()
1595 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); in rv6xx_dpm_enable()
1597 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in rv6xx_dpm_enable()
1599 r600_start_dpm(rdev); in rv6xx_dpm_enable()
1602 rv6xx_enable_static_voltage_control(rdev, boot_ps, false); in rv6xx_dpm_enable()
1605 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true); in rv6xx_dpm_enable()
1608 r600_gfx_clockgating_enable(rdev, true); in rv6xx_dpm_enable()
1613 void rv6xx_dpm_disable(struct radeon_device *rdev) in rv6xx_dpm_disable() argument
1615 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_disable()
1616 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_disable()
1618 if (!r600_dynamicpm_enabled(rdev)) in rv6xx_dpm_disable()
1621 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_disable()
1622 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_disable()
1623 rv6xx_enable_display_gap(rdev, false); in rv6xx_dpm_disable()
1624 rv6xx_clear_vc(rdev); in rv6xx_dpm_disable()
1625 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_disable()
1628 r600_enable_thermal_protection(rdev, false); in rv6xx_dpm_disable()
1630 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_disable()
1631 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_disable()
1632 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_disable()
1634 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_disable()
1635 rv6xx_enable_backbias(rdev, false); in rv6xx_dpm_disable()
1637 rv6xx_enable_spread_spectrum(rdev, false); in rv6xx_dpm_disable()
1640 rv6xx_enable_static_voltage_control(rdev, boot_ps, true); in rv6xx_dpm_disable()
1643 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false); in rv6xx_dpm_disable()
1645 if (rdev->irq.installed && in rv6xx_dpm_disable()
1646 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in rv6xx_dpm_disable()
1647 rdev->irq.dpm_thermal = false; in rv6xx_dpm_disable()
1648 radeon_irq_set(rdev); in rv6xx_dpm_disable()
1652 r600_gfx_clockgating_enable(rdev, false); in rv6xx_dpm_disable()
1654 r600_stop_dpm(rdev); in rv6xx_dpm_disable()
1657 int rv6xx_dpm_set_power_state(struct radeon_device *rdev) in rv6xx_dpm_set_power_state() argument
1659 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_set_power_state()
1660 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rv6xx_dpm_set_power_state()
1661 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rv6xx_dpm_set_power_state()
1666 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1668 rv6xx_clear_vc(rdev); in rv6xx_dpm_set_power_state()
1669 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_set_power_state()
1670 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_set_power_state()
1673 r600_enable_thermal_protection(rdev, false); in rv6xx_dpm_set_power_state()
1675 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1676 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_set_power_state()
1677 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_set_power_state()
1679 rv6xx_generate_transition_stepping(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1680 rv6xx_program_power_level_medium_for_transition(rdev); in rv6xx_dpm_set_power_state()
1683 rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1684 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv6xx_dpm_set_power_state()
1685 rv6xx_set_sw_voltage_to_low(rdev, old_ps); in rv6xx_dpm_set_power_state()
1688 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1689 rv6xx_set_safe_backbias(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1692 rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1695 rv6xx_enable_dynamic_voltage_control(rdev, false); in rv6xx_dpm_set_power_state()
1697 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1698 rv6xx_enable_dynamic_backbias_control(rdev, false); in rv6xx_dpm_set_power_state()
1701 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv6xx_dpm_set_power_state()
1702 rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1703 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_dpm_set_power_state()
1706 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_set_power_state()
1707 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_dpm_set_power_state()
1708 r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1710 rv6xx_generate_low_step(rdev, new_ps); in rv6xx_dpm_set_power_state()
1711 rv6xx_invalidate_intermediate_steps(rdev); in rv6xx_dpm_set_power_state()
1712 rv6xx_calculate_stepping_parameters(rdev, new_ps); in rv6xx_dpm_set_power_state()
1713 rv6xx_program_stepping_parameters_lowest_entry(rdev); in rv6xx_dpm_set_power_state()
1714 rv6xx_program_power_level_low_to_lowest_state(rdev); in rv6xx_dpm_set_power_state()
1716 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_set_power_state()
1717 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1718 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_set_power_state()
1721 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) { in rv6xx_dpm_set_power_state()
1722 ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1726 rv6xx_enable_dynamic_voltage_control(rdev, true); in rv6xx_dpm_set_power_state()
1729 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1730 rv6xx_enable_dynamic_backbias_control(rdev, true); in rv6xx_dpm_set_power_state()
1733 rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true); in rv6xx_dpm_set_power_state()
1735 rv6xx_reset_lvtm_data_sync(rdev); in rv6xx_dpm_set_power_state()
1737 rv6xx_generate_stepping_table(rdev, new_ps); in rv6xx_dpm_set_power_state()
1738 rv6xx_program_stepping_parameters_except_lowest_entry(rdev); in rv6xx_dpm_set_power_state()
1739 rv6xx_program_power_level_low(rdev); in rv6xx_dpm_set_power_state()
1740 rv6xx_program_power_level_medium(rdev); in rv6xx_dpm_set_power_state()
1741 rv6xx_program_power_level_high(rdev); in rv6xx_dpm_set_power_state()
1742 rv6xx_enable_medium(rdev); in rv6xx_dpm_set_power_state()
1743 rv6xx_enable_high(rdev); in rv6xx_dpm_set_power_state()
1746 rv6xx_enable_thermal_protection(rdev, true); in rv6xx_dpm_set_power_state()
1747 rv6xx_program_vc(rdev); in rv6xx_dpm_set_power_state()
1748 rv6xx_program_at(rdev); in rv6xx_dpm_set_power_state()
1750 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1755 void rv6xx_setup_asic(struct radeon_device *rdev) in rv6xx_setup_asic() argument
1757 r600_enable_acpi_pm(rdev); in rv6xx_setup_asic()
1760 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) in rv6xx_setup_asic()
1761 rv6xx_enable_l0s(rdev); in rv6xx_setup_asic()
1762 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) in rv6xx_setup_asic()
1763 rv6xx_enable_l1(rdev); in rv6xx_setup_asic()
1764 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) in rv6xx_setup_asic()
1765 rv6xx_enable_pll_sleep_in_l1(rdev); in rv6xx_setup_asic()
1769 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev) in rv6xx_dpm_display_configuration_changed() argument
1771 rv6xx_program_display_gap(rdev); in rv6xx_dpm_display_configuration_changed()
1795 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev, in rv6xx_parse_pplib_non_clock_info() argument
1812 rdev->pm.dpm.boot_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1814 rdev->pm.dpm.uvd_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1817 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev, in rv6xx_parse_pplib_clock_info() argument
1851 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0) in rv6xx_parse_pplib_clock_info()
1857 if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) { in rv6xx_parse_pplib_clock_info()
1866 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in rv6xx_parse_pplib_clock_info()
1867 pl->mclk = rdev->clock.default_mclk; in rv6xx_parse_pplib_clock_info()
1868 pl->sclk = rdev->clock.default_sclk; in rv6xx_parse_pplib_clock_info()
1873 static int rv6xx_parse_power_table(struct radeon_device *rdev) in rv6xx_parse_power_table() argument
1875 struct radeon_mode_info *mode_info = &rdev->mode_info; in rv6xx_parse_power_table()
1891 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in rv6xx_parse_power_table()
1893 if (!rdev->pm.dpm.ps) in rv6xx_parse_power_table()
1910 kfree(rdev->pm.dpm.ps); in rv6xx_parse_power_table()
1913 rdev->pm.dpm.ps[i].ps_priv = ps; in rv6xx_parse_power_table()
1914 rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in rv6xx_parse_power_table()
1922 rv6xx_parse_pplib_clock_info(rdev, in rv6xx_parse_power_table()
1923 &rdev->pm.dpm.ps[i], j, in rv6xx_parse_power_table()
1928 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; in rv6xx_parse_power_table()
1932 int rv6xx_dpm_init(struct radeon_device *rdev) in rv6xx_dpm_init() argument
1942 rdev->pm.dpm.priv = pi; in rv6xx_dpm_init()
1944 ret = r600_get_platform_caps(rdev); in rv6xx_dpm_init()
1948 ret = rv6xx_parse_power_table(rdev); in rv6xx_dpm_init()
1952 if (rdev->pm.dpm.voltage_response_time == 0) in rv6xx_dpm_init()
1953 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in rv6xx_dpm_init()
1954 if (rdev->pm.dpm.backbias_response_time == 0) in rv6xx_dpm_init()
1955 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in rv6xx_dpm_init()
1957 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in rv6xx_dpm_init()
1964 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, in rv6xx_dpm_init()
1971 if (rdev->family >= CHIP_RV670) in rv6xx_dpm_init()
1977 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); in rv6xx_dpm_init()
1981 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_dpm_init()
1983 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_dpm_init()
1997 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) in rv6xx_dpm_init()
2007 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, in rv6xx_dpm_print_power_state() argument
2025 r600_dpm_print_ps_status(rdev, rps); in rv6xx_dpm_print_power_state()
2028 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in rv6xx_dpm_debugfs_print_current_performance_level() argument
2031 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_debugfs_print_current_performance_level()
2054 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev) in rv6xx_dpm_get_current_sclk() argument
2056 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_get_current_sclk()
2077 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev) in rv6xx_dpm_get_current_mclk() argument
2079 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_get_current_mclk()
2099 void rv6xx_dpm_fini(struct radeon_device *rdev) in rv6xx_dpm_fini() argument
2103 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in rv6xx_dpm_fini()
2104 kfree(rdev->pm.dpm.ps[i].ps_priv); in rv6xx_dpm_fini()
2106 kfree(rdev->pm.dpm.ps); in rv6xx_dpm_fini()
2107 kfree(rdev->pm.dpm.priv); in rv6xx_dpm_fini()
2110 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low) in rv6xx_dpm_get_sclk() argument
2112 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); in rv6xx_dpm_get_sclk()
2120 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low) in rv6xx_dpm_get_mclk() argument
2122 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); in rv6xx_dpm_get_mclk()
2130 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, in rv6xx_dpm_force_performance_level() argument
2133 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_force_performance_level()
2143 rv6xx_clear_vc(rdev); in rv6xx_dpm_force_performance_level()
2144 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_force_performance_level()
2145 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_force_performance_level()
2146 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_force_performance_level()
2147 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_force_performance_level()
2148 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_force_performance_level()
2149 rv6xx_enable_medium(rdev); in rv6xx_dpm_force_performance_level()
2150 rv6xx_enable_high(rdev); in rv6xx_dpm_force_performance_level()
2152 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_dpm_force_performance_level()
2153 rv6xx_program_vc(rdev); in rv6xx_dpm_force_performance_level()
2154 rv6xx_program_at(rdev); in rv6xx_dpm_force_performance_level()
2156 rdev->pm.dpm.forced_level = level; in rv6xx_dpm_force_performance_level()