38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 static void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
49 void rv515_debugfs(struct radeon_device *rdev)  in rv515_debugfs()  argument
51 	if (r100_debugfs_rbbm_init(rdev)) {  in rv515_debugfs()
54 	if (rv515_debugfs_pipes_info_init(rdev)) {  in rv515_debugfs()
57 	if (rv515_debugfs_ga_info_init(rdev)) {  in rv515_debugfs()
62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)  in rv515_ring_start()  argument
66 	r = radeon_ring_lock(rdev, ring, 64);  in rv515_ring_start()
85 	radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);  in rv515_ring_start()
127 	radeon_ring_unlock_commit(rdev, ring, false);  in rv515_ring_start()
130 int rv515_mc_wait_for_idle(struct radeon_device *rdev)  in rv515_mc_wait_for_idle()  argument
135 	for (i = 0; i < rdev->usec_timeout; i++) {  in rv515_mc_wait_for_idle()
146 void rv515_vga_render_disable(struct radeon_device *rdev)  in rv515_vga_render_disable()  argument
152 static void rv515_gpu_init(struct radeon_device *rdev)  in rv515_gpu_init()  argument
156 	if (r100_gui_wait_for_idle(rdev)) {  in rv515_gpu_init()
160 	rv515_vga_render_disable(rdev);  in rv515_gpu_init()
161 	r420_pipes_init(rdev);  in rv515_gpu_init()
168 	if (r100_gui_wait_for_idle(rdev)) {  in rv515_gpu_init()
172 	if (rv515_mc_wait_for_idle(rdev)) {  in rv515_gpu_init()
178 static void rv515_vram_get_type(struct radeon_device *rdev)  in rv515_vram_get_type()  argument
182 	rdev->mc.vram_width = 128;  in rv515_vram_get_type()
183 	rdev->mc.vram_is_ddr = true;  in rv515_vram_get_type()
187 		rdev->mc.vram_width = 64;  in rv515_vram_get_type()
190 		rdev->mc.vram_width = 128;  in rv515_vram_get_type()
193 		rdev->mc.vram_width = 128;  in rv515_vram_get_type()
198 static void rv515_mc_init(struct radeon_device *rdev)  in rv515_mc_init()  argument
201 	rv515_vram_get_type(rdev);  in rv515_mc_init()
202 	r100_vram_init_sizes(rdev);  in rv515_mc_init()
203 	radeon_vram_location(rdev, &rdev->mc, 0);  in rv515_mc_init()
204 	rdev->mc.gtt_base_align = 0;  in rv515_mc_init()
205 	if (!(rdev->flags & RADEON_IS_AGP))  in rv515_mc_init()
206 		radeon_gtt_location(rdev, &rdev->mc);  in rv515_mc_init()
207 	radeon_update_bandwidth_info(rdev);  in rv515_mc_init()
210 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)  in rv515_mc_rreg()  argument
215 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rv515_mc_rreg()
219 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rv515_mc_rreg()
224 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)  in rv515_mc_wreg()  argument
228 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rv515_mc_wreg()
232 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rv515_mc_wreg()
240 	struct radeon_device *rdev = dev->dev_private;  in rv515_debugfs_pipes_info()  local
258 	struct radeon_device *rdev = dev->dev_private;  in rv515_debugfs_ga_info()  local
263 	radeon_asic_reset(rdev);  in rv515_debugfs_ga_info()
278 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)  in rv515_debugfs_pipes_info_init()  argument
281 	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);  in rv515_debugfs_pipes_info_init()
287 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)  in rv515_debugfs_ga_info_init()  argument
290 	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);  in rv515_debugfs_ga_info_init()
296 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)  in rv515_mc_stop()  argument
307 	for (i = 0; i < rdev->num_crtc; i++) {  in rv515_mc_stop()
313 				radeon_wait_for_vblank(rdev, i);  in rv515_mc_stop()
320 			frame_count = radeon_get_vblank_counter(rdev, i);  in rv515_mc_stop()
321 			for (j = 0; j < rdev->usec_timeout; j++) {  in rv515_mc_stop()
322 				if (radeon_get_vblank_counter(rdev, i) != frame_count)  in rv515_mc_stop()
340 	radeon_mc_wait_for_idle(rdev);  in rv515_mc_stop()
342 	if (rdev->family >= CHIP_R600) {  in rv515_mc_stop()
343 		if (rdev->family >= CHIP_RV770)  in rv515_mc_stop()
352 			if (rdev->family >= CHIP_RV770)  in rv515_mc_stop()
362 	for (i = 0; i < rdev->num_crtc; i++) {  in rv515_mc_stop()
378 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)  in rv515_mc_resume()  argument
384 	for (i = 0; i < rdev->num_crtc; i++) {  in rv515_mc_resume()
385 		if (rdev->family >= CHIP_RV770) {  in rv515_mc_resume()
388 				       upper_32_bits(rdev->mc.vram_start));  in rv515_mc_resume()
390 				       upper_32_bits(rdev->mc.vram_start));  in rv515_mc_resume()
393 				       upper_32_bits(rdev->mc.vram_start));  in rv515_mc_resume()
395 				       upper_32_bits(rdev->mc.vram_start));  in rv515_mc_resume()
399 		       (u32)rdev->mc.vram_start);  in rv515_mc_resume()
401 		       (u32)rdev->mc.vram_start);  in rv515_mc_resume()
403 	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);  in rv515_mc_resume()
406 	for (i = 0; i < rdev->num_crtc; i++) {  in rv515_mc_resume()
424 			for (j = 0; j < rdev->usec_timeout; j++) {  in rv515_mc_resume()
433 	if (rdev->family >= CHIP_R600) {  in rv515_mc_resume()
435 		if (rdev->family >= CHIP_RV770)  in rv515_mc_resume()
440 		if (rdev->family >= CHIP_RV770)  in rv515_mc_resume()
448 	for (i = 0; i < rdev->num_crtc; i++) {  in rv515_mc_resume()
454 			frame_count = radeon_get_vblank_counter(rdev, i);  in rv515_mc_resume()
455 			for (j = 0; j < rdev->usec_timeout; j++) {  in rv515_mc_resume()
456 				if (radeon_get_vblank_counter(rdev, i) != frame_count)  in rv515_mc_resume()
468 static void rv515_mc_program(struct radeon_device *rdev)  in rv515_mc_program()  argument
473 	rv515_mc_stop(rdev, &save);  in rv515_mc_program()
476 	if (rv515_mc_wait_for_idle(rdev))  in rv515_mc_program()
477 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");  in rv515_mc_program()
479 	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);  in rv515_mc_program()
482 			S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |  in rv515_mc_program()
483 			S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));  in rv515_mc_program()
485 		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));  in rv515_mc_program()
486 	if (rdev->flags & RADEON_IS_AGP) {  in rv515_mc_program()
488 			S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |  in rv515_mc_program()
489 			S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));  in rv515_mc_program()
490 		WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));  in rv515_mc_program()
492 			S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));  in rv515_mc_program()
499 	rv515_mc_resume(rdev, &save);  in rv515_mc_program()
502 void rv515_clock_startup(struct radeon_device *rdev)  in rv515_clock_startup()  argument
505 		radeon_atom_set_clock_gating(rdev, 1);  in rv515_clock_startup()
515 static int rv515_startup(struct radeon_device *rdev)  in rv515_startup()  argument
519 	rv515_mc_program(rdev);  in rv515_startup()
521 	rv515_clock_startup(rdev);  in rv515_startup()
523 	rv515_gpu_init(rdev);  in rv515_startup()
526 	if (rdev->flags & RADEON_IS_PCIE) {  in rv515_startup()
527 		r = rv370_pcie_gart_enable(rdev);  in rv515_startup()
533 	r = radeon_wb_init(rdev);  in rv515_startup()
537 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);  in rv515_startup()
539 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in rv515_startup()
544 	if (!rdev->irq.installed) {  in rv515_startup()
545 		r = radeon_irq_kms_init(rdev);  in rv515_startup()
550 	rs600_irq_set(rdev);  in rv515_startup()
551 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in rv515_startup()
553 	r = r100_cp_init(rdev, 1024 * 1024);  in rv515_startup()
555 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);  in rv515_startup()
559 	r = radeon_ib_pool_init(rdev);  in rv515_startup()
561 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in rv515_startup()
568 int rv515_resume(struct radeon_device *rdev)  in rv515_resume()  argument
573 	if (rdev->flags & RADEON_IS_PCIE)  in rv515_resume()
574 		rv370_pcie_gart_disable(rdev);  in rv515_resume()
576 	rv515_clock_startup(rdev);  in rv515_resume()
578 	if (radeon_asic_reset(rdev)) {  in rv515_resume()
579 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in rv515_resume()
584 	atom_asic_init(rdev->mode_info.atom_context);  in rv515_resume()
586 	rv515_clock_startup(rdev);  in rv515_resume()
588 	radeon_surface_init(rdev);  in rv515_resume()
590 	rdev->accel_working = true;  in rv515_resume()
591 	r =  rv515_startup(rdev);  in rv515_resume()
593 		rdev->accel_working = false;  in rv515_resume()
598 int rv515_suspend(struct radeon_device *rdev)  in rv515_suspend()  argument
600 	radeon_pm_suspend(rdev);  in rv515_suspend()
601 	r100_cp_disable(rdev);  in rv515_suspend()
602 	radeon_wb_disable(rdev);  in rv515_suspend()
603 	rs600_irq_disable(rdev);  in rv515_suspend()
604 	if (rdev->flags & RADEON_IS_PCIE)  in rv515_suspend()
605 		rv370_pcie_gart_disable(rdev);  in rv515_suspend()
609 void rv515_set_safe_registers(struct radeon_device *rdev)  in rv515_set_safe_registers()  argument
611 	rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;  in rv515_set_safe_registers()
612 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);  in rv515_set_safe_registers()
615 void rv515_fini(struct radeon_device *rdev)  in rv515_fini()  argument
617 	radeon_pm_fini(rdev);  in rv515_fini()
618 	r100_cp_fini(rdev);  in rv515_fini()
619 	radeon_wb_fini(rdev);  in rv515_fini()
620 	radeon_ib_pool_fini(rdev);  in rv515_fini()
621 	radeon_gem_fini(rdev);  in rv515_fini()
622 	rv370_pcie_gart_fini(rdev);  in rv515_fini()
623 	radeon_agp_fini(rdev);  in rv515_fini()
624 	radeon_irq_kms_fini(rdev);  in rv515_fini()
625 	radeon_fence_driver_fini(rdev);  in rv515_fini()
626 	radeon_bo_fini(rdev);  in rv515_fini()
627 	radeon_atombios_fini(rdev);  in rv515_fini()
628 	kfree(rdev->bios);  in rv515_fini()
629 	rdev->bios = NULL;  in rv515_fini()
632 int rv515_init(struct radeon_device *rdev)  in rv515_init()  argument
637 	radeon_scratch_init(rdev);  in rv515_init()
639 	radeon_surface_init(rdev);  in rv515_init()
642 	r100_restore_sanity(rdev);  in rv515_init()
644 	if (!radeon_get_bios(rdev)) {  in rv515_init()
645 		if (ASIC_IS_AVIVO(rdev))  in rv515_init()
648 	if (rdev->is_atom_bios) {  in rv515_init()
649 		r = radeon_atombios_init(rdev);  in rv515_init()
653 		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");  in rv515_init()
657 	if (radeon_asic_reset(rdev)) {  in rv515_init()
658 		dev_warn(rdev->dev,  in rv515_init()
664 	if (radeon_boot_test_post_card(rdev) == false)  in rv515_init()
667 	radeon_get_clock_info(rdev->ddev);  in rv515_init()
669 	if (rdev->flags & RADEON_IS_AGP) {  in rv515_init()
670 		r = radeon_agp_init(rdev);  in rv515_init()
672 			radeon_agp_disable(rdev);  in rv515_init()
676 	rv515_mc_init(rdev);  in rv515_init()
677 	rv515_debugfs(rdev);  in rv515_init()
679 	r = radeon_fence_driver_init(rdev);  in rv515_init()
683 	r = radeon_bo_init(rdev);  in rv515_init()
686 	r = rv370_pcie_gart_init(rdev);  in rv515_init()
689 	rv515_set_safe_registers(rdev);  in rv515_init()
692 	radeon_pm_init(rdev);  in rv515_init()
694 	rdev->accel_working = true;  in rv515_init()
695 	r = rv515_startup(rdev);  in rv515_init()
698 		dev_err(rdev->dev, "Disabling GPU acceleration\n");  in rv515_init()
699 		r100_cp_fini(rdev);  in rv515_init()
700 		radeon_wb_fini(rdev);  in rv515_init()
701 		radeon_ib_pool_fini(rdev);  in rv515_init()
702 		radeon_irq_kms_fini(rdev);  in rv515_init()
703 		rv370_pcie_gart_fini(rdev);  in rv515_init()
704 		radeon_agp_fini(rdev);  in rv515_init()
705 		rdev->accel_working = false;  in rv515_init()
710 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)  in atom_rv515_force_tv_scaler()  argument
953 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,  in rv515_crtc_bandwidth_compute()  argument
972 	if ((rdev->family >= CHIP_RV610) &&  in rv515_crtc_bandwidth_compute()
973 	    (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)  in rv515_crtc_bandwidth_compute()
974 		selected_sclk = radeon_dpm_get_sclk(rdev, low);  in rv515_crtc_bandwidth_compute()
976 		selected_sclk = rdev->pm.current_sclk;  in rv515_crtc_bandwidth_compute()
1109 static void rv515_compute_mode_priority(struct radeon_device *rdev,  in rv515_compute_mode_priority()  argument
1172 		if (rdev->disp_priority == 2) {  in rv515_compute_mode_priority()
1201 		if (rdev->disp_priority == 2)  in rv515_compute_mode_priority()
1228 		if (rdev->disp_priority == 2)  in rv515_compute_mode_priority()
1233 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)  in rv515_bandwidth_avivo_update()  argument
1243 	if (rdev->mode_info.crtcs[0]->base.enabled)  in rv515_bandwidth_avivo_update()
1244 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;  in rv515_bandwidth_avivo_update()
1245 	if (rdev->mode_info.crtcs[1]->base.enabled)  in rv515_bandwidth_avivo_update()
1246 		mode1 = &rdev->mode_info.crtcs[1]->base.mode;  in rv515_bandwidth_avivo_update()
1247 	rs690_line_buffer_adjust(rdev, mode0, mode1);  in rv515_bandwidth_avivo_update()
1249 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);  in rv515_bandwidth_avivo_update()
1250 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);  in rv515_bandwidth_avivo_update()
1252 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);  in rv515_bandwidth_avivo_update()
1253 	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);  in rv515_bandwidth_avivo_update()
1259 	rv515_compute_mode_priority(rdev,  in rv515_bandwidth_avivo_update()
1263 	rv515_compute_mode_priority(rdev,  in rv515_bandwidth_avivo_update()
1274 void rv515_bandwidth_update(struct radeon_device *rdev)  in rv515_bandwidth_update()  argument
1280 	if (!rdev->mode_info.mode_config_initialized)  in rv515_bandwidth_update()
1283 	radeon_update_display_priority(rdev);  in rv515_bandwidth_update()
1285 	if (rdev->mode_info.crtcs[0]->base.enabled)  in rv515_bandwidth_update()
1286 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;  in rv515_bandwidth_update()
1287 	if (rdev->mode_info.crtcs[1]->base.enabled)  in rv515_bandwidth_update()
1288 		mode1 = &rdev->mode_info.crtcs[1]->base.mode;  in rv515_bandwidth_update()
1294 	if ((rdev->disp_priority == 2) &&  in rv515_bandwidth_update()
1295 	    (rdev->family == CHIP_RV515)) {  in rv515_bandwidth_update()
1305 	rv515_bandwidth_avivo_update(rdev);  in rv515_bandwidth_update()