116 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rs600_page_flip()  local
120 	tmp |= AVIVO_D1GRPH_UPDATE_LOCK;  in rs600_page_flip()
121 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
138 	tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;  in rs600_page_flip()
139 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
158 	u32 tmp = 0;  in avivo_program_fmt()  local
178 			tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;  in avivo_program_fmt()
180 			tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;  in avivo_program_fmt()
185 			tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |  in avivo_program_fmt()
188 			tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |  in avivo_program_fmt()
199 		WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
202 		WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
205 		WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
208 		WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
220 	u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;  in rs600_pm_misc()  local
225 			tmp = RREG32(voltage->gpio.reg);  in rs600_pm_misc()
227 				tmp |= voltage->gpio.mask;  in rs600_pm_misc()
229 				tmp &= ~(voltage->gpio.mask);  in rs600_pm_misc()
230 			WREG32(voltage->gpio.reg, tmp);  in rs600_pm_misc()
234 			tmp = RREG32(voltage->gpio.reg);  in rs600_pm_misc()
236 				tmp &= ~voltage->gpio.mask;  in rs600_pm_misc()
238 				tmp |= voltage->gpio.mask;  in rs600_pm_misc()
239 			WREG32(voltage->gpio.reg, tmp);  in rs600_pm_misc()
314 	u32 tmp;  in rs600_pm_prepare()  local
320 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_prepare()
321 			tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;  in rs600_pm_prepare()
322 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_prepare()
332 	u32 tmp;  in rs600_pm_finish()  local
338 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_finish()
339 			tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;  in rs600_pm_finish()
340 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_finish()
348 	u32 tmp;  in rs600_hpd_sense()  local
353 		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);  in rs600_hpd_sense()
354 		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))  in rs600_hpd_sense()
358 		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);  in rs600_hpd_sense()
359 		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))  in rs600_hpd_sense()
371 	u32 tmp;  in rs600_hpd_set_polarity()  local
376 		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);  in rs600_hpd_set_polarity()
378 			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);  in rs600_hpd_set_polarity()
380 			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);  in rs600_hpd_set_polarity()
381 		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in rs600_hpd_set_polarity()
384 		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);  in rs600_hpd_set_polarity()
386 			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);  in rs600_hpd_set_polarity()
388 			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);  in rs600_hpd_set_polarity()
389 		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in rs600_hpd_set_polarity()
450 	u32 status, tmp;  in rs600_asic_reset()  local
463 	tmp = RREG32(RADEON_CP_RB_CNTL);  in rs600_asic_reset()
464 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);  in rs600_asic_reset()
467 	WREG32(RADEON_CP_RB_CNTL, tmp);  in rs600_asic_reset()
514 	uint32_t tmp;  in rs600_gart_tlb_flush()  local
516 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);  in rs600_gart_tlb_flush()
517 	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;  in rs600_gart_tlb_flush()
518 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);  in rs600_gart_tlb_flush()
520 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);  in rs600_gart_tlb_flush()
521 	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);  in rs600_gart_tlb_flush()
522 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);  in rs600_gart_tlb_flush()
524 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);  in rs600_gart_tlb_flush()
525 	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;  in rs600_gart_tlb_flush()
526 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);  in rs600_gart_tlb_flush()
527 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);  in rs600_gart_tlb_flush()
549 	u32 tmp;  in rs600_gart_enable()  local
560 	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;  in rs600_gart_enable()
561 	WREG32(RADEON_BUS_CNTL, tmp);  in rs600_gart_enable()
599 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);  in rs600_gart_enable()
600 	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));  in rs600_gart_enable()
601 	tmp = RREG32_MC(R_000009_MC_CNTL1);  in rs600_gart_enable()
602 	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));  in rs600_gart_enable()
613 	u32 tmp;  in rs600_gart_disable()  local
617 	tmp = RREG32_MC(R_000009_MC_CNTL1);  in rs600_gart_disable()
618 	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);  in rs600_gart_disable()
653 	uint32_t tmp = 0;  in rs600_irq_set()  local
672 		tmp |= S_000040_SW_INT_EN(1);  in rs600_irq_set()
691 	WREG32(R_000040_GEN_INT_CNTL, tmp);  in rs600_irq_set()
708 	u32 tmp;  in rs600_irq_ack()  local
721 			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);  in rs600_irq_ack()
722 			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);  in rs600_irq_ack()
723 			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in rs600_irq_ack()
726 			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);  in rs600_irq_ack()
727 			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);  in rs600_irq_ack()
728 			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in rs600_irq_ack()
738 			tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);  in rs600_irq_ack()
739 			tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);  in rs600_irq_ack()
740 			WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);  in rs600_irq_ack()