121 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
124 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
126 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
139 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
199 		WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
202 		WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
205 		WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
208 		WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);  in avivo_program_fmt()
230 			WREG32(voltage->gpio.reg, tmp);  in rs600_pm_misc()
239 			WREG32(voltage->gpio.reg, tmp);  in rs600_pm_misc()
322 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_prepare()
340 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_finish()
381 		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in rs600_hpd_set_polarity()
389 		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in rs600_hpd_set_polarity()
406 			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,  in rs600_hpd_init()
410 			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,  in rs600_hpd_init()
432 			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,  in rs600_hpd_fini()
436 			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,  in rs600_hpd_fini()
462 	WREG32(RADEON_CP_CSQ_CNTL, 0);  in rs600_asic_reset()
464 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);  in rs600_asic_reset()
465 	WREG32(RADEON_CP_RB_RPTR_WR, 0);  in rs600_asic_reset()
466 	WREG32(RADEON_CP_RB_WPTR, 0);  in rs600_asic_reset()
467 	WREG32(RADEON_CP_RB_CNTL, tmp);  in rs600_asic_reset()
473 	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |  in rs600_asic_reset()
477 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in rs600_asic_reset()
482 	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));  in rs600_asic_reset()
485 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in rs600_asic_reset()
490 	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));  in rs600_asic_reset()
493 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in rs600_asic_reset()
561 	WREG32(RADEON_BUS_CNTL, tmp);  in rs600_gart_enable()
668 		WREG32(R_000040_GEN_INT_CNTL, 0);  in rs600_irq_set()
691 	WREG32(R_000040_GEN_INT_CNTL, tmp);  in rs600_irq_set()
692 	WREG32(R_006540_DxMODE_INT_MASK, mode_int);  in rs600_irq_set()
693 	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);  in rs600_irq_set()
694 	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);  in rs600_irq_set()
696 		WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);  in rs600_irq_set()
713 			WREG32(R_006534_D1MODE_VBLANK_STATUS,  in rs600_irq_ack()
717 			WREG32(R_006D34_D2MODE_VBLANK_STATUS,  in rs600_irq_ack()
723 			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in rs600_irq_ack()
728 			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in rs600_irq_ack()
740 			WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);  in rs600_irq_ack()
746 		WREG32(R_000044_GEN_INT_STATUS, irqs);  in rs600_irq_ack()
755 	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);  in rs600_irq_disable()
756 	WREG32(R_000040_GEN_INT_CNTL, 0);  in rs600_irq_disable()
757 	WREG32(R_006540_DxMODE_INT_MASK, 0);  in rs600_irq_disable()
825 			WREG32(RADEON_BUS_CNTL, msi_rearm);  in rs600_irq_process()
826 			WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);  in rs600_irq_process()
829 			WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);  in rs600_irq_process()
908 		WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);  in rs600_bandwidth_update()
909 		WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);  in rs600_bandwidth_update()
910 		WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);  in rs600_bandwidth_update()
911 		WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);  in rs600_bandwidth_update()
921 	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |  in rs600_mc_rreg()
933 	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |  in rs600_mc_wreg()
935 	WREG32(R_000074_MC_IND_DATA, v);  in rs600_mc_wreg()
970 	WREG32(R_000134_HDP_FB_LOCATION,  in rs600_mc_program()